Confirm Memory Detail of 70261L15PFG

Hi,

As I will be taping out a chip recently, I want to confirm some details with your team regarding the SRAM Verilog behavioral model file you provided.

verilog_model.zip

The product I purchased is 70261L15PFG (https://www.mouser.tw/ProductDetail/), and you previously informed me that the Verilog model for 7025 is compatible with this product. However, there are many related parameters to configure in the config.idt7025 file. Therefore, I would like to ask for your assistance in confirming that the settings in my current file (above) are compatible with the 70261L15PFG.

Another part is about when there are some unknowns in the input signal (as shown in the figure), will it cause any port to be forcibly locked? I know that if I open both ports simultaneously and they have the same address, SRAM will forcibly lock one of the ports, and it seems that it won't reopen after changing addresses unless control signals are changed to return to normal operation. I'm not sure if this is a problem with the behavior model or if the actual SRAM operates like this.
Therefore, I want to ask about situations like those in the figure where some control signals may be unknown for a short time, or both ports' addresses become unknown at the same time, whether this would cause a port to be locked during actual operation. (Currently, under this situation from simulation, SRAM operates without problems.)

Thank you very much for your response!

Best,
Jason Shih