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SpiNor AT25FF321A Quad mode

RA_WT

Hello,

I am working on the driver for SpiNor AT25FF321A. I tried to set the Quad Enable (QE) bit in Status Register 2. But it seems not successful. The steps are as follows:

  1. Command 06h  - Write Enable
  2. Command 01h, data 00h - Write 0 to Status Register 1
  3. Command 06h - Write Enable
  4. Command 31h, data 02h - Write 02h to Status Register 2
  5. Command 05h - Read Status Register 1 for 1 byte and verify BP2:0 is 000
  6. Command 35h - Read Status Register 2 for 1 byte and verify the value is 02h

But in step 6, the value read back is 0. I tried to repeat the read every 1msec. 02h still cannot be seen.

After step 6 when I read the SpiNor memory using 6Bh (Quad Output Read Array), it always gives a fixed pattern 0xDD, and sometimes it is 0x11.

  • 0

    Hi There,

    Thank you for posting your question online and apologies for the delay.
    Let me check on this and I will get back to you as soon as possible.

    Best Regards,
    OV_Renesas

  • 0

    Hello,

    It sounds like you're encountering a tricky issue with setting the Quad Enable (QE) bit on the SpiNor AT25FF321A. Here are a few things you might want to check:

    Write Enable Command: Ensure that the Write Enable command (06h) is successfully executed before attempting to write to the status registers. You can verify this by reading the status register to check if the Write Enable Latch (WEL) bit is set.

    Timing and Delays: Sometimes, timing issues can cause problems. Make sure there is sufficient delay between commands, especially after the Write Enable command. You mentioned a 1ms delay, but you might want to experiment with slightly longer delays.

    Status Register Verification: After writing to Status Register 2, verify if the write was successful by reading back the register immediately. If the value is not as expected, it might indicate an issue with the write process.

    Power Cycle: Some devices require a power cycle after setting certain bits. Try power cycling the device after setting the QE bit and then check the status register again.

    Manufacturer-Specific Procedures: The procedure to set the QE bit can vary between different memory models and manufacturers. Make sure you are following the specific procedure for the AT25FF321A. You can refer to the Microchip documentation for more details.

    Fixed Pattern Issue: The fixed pattern (0xDD or 0x11) you are seeing might indicate that the QE bit is not set correctly, causing the device to operate in a different mode. Double-check the commands and ensure that the QE bit is being set properly.

    Hope this helps!

    Best regards,
    Elena Brown
    Summit Medical Group

  • +1 in reply to elena56brown

    Yes, after writing the configuration for QE, it should for RDY bit set. I have tried out. Thanks for the information.