while creating project on controller R7F7016483AFP We see RAM Size as below
Local RAM (192)k+ Global A(64)k+ Global B( 64) k+ retention RAM (64)k = 384K RAM ( don’t see Self RAM here, as per website, it is right )
In Datasheet : RAM Allocation is like :
Local CPU RAM( 192) + Local self(192) + Global A(64)k+ Global B( 64) k+ retention RAM (64)k = 576K RAM
we are is using R7F7016483AFP part with max frequency 240Mhz, 384K RAM, 3MB Flash.
we have allocated RAM Self RAM for FCL. If self RAM is in controller then total RAM is 576K RAM. If not then calculation is rite without Self RAM. now we are facing issues.
can you share any document regarding self RAM in RH850 controller.
Self-RAM is the local-CPU RAM, it is duplicated / mirrored in the address space so that multiple cores can execute the same common code but maintain separate data spaces.
If the local RAM needs to be shared by multiple cores or bus masters (e.g. DMA), it should be mapped using the non-self / "CPU" area.
it means if CPU RAM is full, then we cannot use Self RAM.
or if i put fdl in self RAM and same time if CPU1 RAM increases then it may crate problem?