The chip I use is RH850-U2A8, and I use an OSTM0 clock as a clock reference to execute the task, and its interrupt interval is 1ms; Now I want to use the OSTM1 clock at the same time to improve the accuracy (1ms is not enough), but when I initialize and use OSTM1 in the same way as OSTM0, there is a problem: the program enters an Unexpected interrupt. For the configuration of OSTM, I used the Davinci Configurator configuration tool and the latest MCAL from Renesas. I have checked the following points:1. When the program just enters the Unexpected interrupt, I check the EIC200 register of OSTM1, the value is 0x60, indicating that EIOV is 1, this value is normal, because the phenomenon is the same as OSTM0;2. I also looked at the OSTM1 configuration and after Gpt_StartTimer(OSTM1_xxxx), the OSTMnCTL register has a value of 0x80, which is also normal.3. I checked the ECM module. If an OSTM1 error occurs, it will report the error to the ECM. I can see the corresponding error in the ECM's ECMmSSTRj register, but I did not find it.
Could it be that there are limitations to using multiple OSTM clocks at the same time, but I didn't find that described in the chip manual. I was hoping someone would give me a direction to look.
What do you mean by, "the program enters an Unexpected interrupt"? Is the OSTM1 interrupt occurring but vectoring to the wrong handler?
What interrupt is being issued (i.e. what address is being vectored)?
My program is with OS, to avoid complications, I took a sample program to test, and only kept OSTM1 and its dependencies. When debugging, if the OSTM1 interrupt function breaks, it will stop at the breakpoint, and then click Run to run the program will run to the non-code location. This means that the OSTM1 interrupt is accessible.If you change OSTM1 to OSTM0, everything works fine
It is still unclear what the 'unexpected interrupt' is. OSTM0 and OSTM1 are almost identical. One difference is that the output mode is only supported from OSTM0 ,OSTM8 and OSTM9.
Also, notifying the ECM of errors when an OSTMn (n = 1 to 9) interrupt occurs - not with OSTM0.
I hope it helps.