RH850 Configuration for I2C communication

Hello ,

         We are using RH850 D1M1A Renesas MCU for developing a cluster for EV(Electronic Vehicle). We are able to display the images on TFT touch display but
not able to receive the touch data from TFT display. The I2C communication used between Renesas and TFT. SIS9509 I2C driver IC is used to retrieve the data from TFT.
       We are tested this TFT with another MCU(STM32) we got Touch data. But communicate with this RH850 MCU it gives NACK. We captured a waveform with these STM32 and RH850 MCUs.
         After comparing these waveforms we observes Clock stretching happen in STM32 MCU but in RH850 doesn’t. We have doubt on how to enable the clock stretching in RH850 registers and is this causes for could not get touch data from TFT?

       
         Kindly guide to get touch data from TFT using SIS9509 I2C driver with RH850. Below attached I2C waveform for your reference.

Software IDE : Multi IDE(GHS).
MCU : RH850D1M1A-R7F701441
TFT Display : TCXD070ABLMT
Touch Driver IC : SIS9509 I2C Driver IC

Parents
  • Hello,

    Clock stretching is a feature of IIC slaves while the RH850 is a IIC master in this case.

    What you need to do should be achieved with the Wait function which can keep SCL low between the ninth clock cycle and the first clock cycle of the next transfer.

    When the WAIT bit is 1, the SCL line is held low from the falling edge of the ninth clock cycle until the
    RIICnDRR value is read each time single-byte data is received. This enables receive operation in byte
    units.

    This function is enabled by setting WAIT bit to 1:

    The WAIT bit are valid only in receive mode.

Reply
  • Hello,

    Clock stretching is a feature of IIC slaves while the RH850 is a IIC master in this case.

    What you need to do should be achieved with the Wait function which can keep SCL low between the ninth clock cycle and the first clock cycle of the next transfer.

    When the WAIT bit is 1, the SCL line is held low from the falling edge of the ninth clock cycle until the
    RIICnDRR value is read each time single-byte data is received. This enables receive operation in byte
    units.

    This function is enabled by setting WAIT bit to 1:

    The WAIT bit are valid only in receive mode.

Children
  • Hello,

       Thanks for your reply.

        We tried like as your reply in IIC initialization (WAIT bit to1). RH850(Master) communicated to that TFT driver IC(Slave) with ACK and We got touch sample data in first time.

        When we read second time after 1s delay it stopped in the master start condition function (below image) . But we need read touch data more times to that TFT.

    Is there need to reset the Register values or Any else to read more times for get touch data. Can you please guide me to overcome the issue.

        

  • Hello,

    Apologies for the delay. Normally you do not need to reset any registers. What is the value of CR2 register ?

    Do you read 1 byte every 1 second ? If yes, then the timeout function may be triggered because the SCL line is held low for too much time. Please check section 21.13.1