Hello.
If you look at the UM manual of RH850F1KM-S1 MCU,As you can see in the captured photo below,The difference between the Min/Max range of the sampling and conversion times in the A/D electrical specifications is written as being quite large.
The customer is requesting confirmation of the factors that cause the variation of the Min/Max times of each (Sampling, Conversion) Time.
1. Please answer why the variation range is so large.
Also, we received other question about whether there is a way to reduce the sampling and conversion time of AD. 2. If you have a solution or a method that you can suggest, please guide us by today.
Thank you.
Best Regards,
David lee.
This range of time (min/max) is determined by the ADCLK. For the first line, at 8MHz min ADCLK the time will be the max 5.75us, while the max ADCLK of 40MHz will be the min conversion time of 1.15us.
The number ADCLKs required is 46-cycles for the highlighted conversion time, multiply this by used ADCLK.
The number of ADCLKs required for the highlighted sample-time is 24-cycles, multiply this by the used ADCLK.
Thanks JimB !!
The ADC (total) conversion time depends on the setting of 1. ADCAnSMPCR.SMPT[7:0] (number of cycles for sampling time) 2. ADCAn clock supply frequency (as defined by CKSCLK_AADCA (ADCA0)) For the fastest conversion time CKSCLK_AADCA should be configured to 40MHz.
A minimum conversion time of 1.15µs per channel based on 40MHz A maximum conversion time of 5.75us per channel based on 8MHz (excluding ScanGroup setupt/finish and excluding usage of external multiplexers).