RH850F1KM-S1 / AD Converter Characteristics SPEC.

Question

Hello. 
 If you look at the UM manual of RH850F1KM-S1 MCU, As you can see in the captured photo below, The difference between the Min/Max range of the sampling and conversion times in the A/D electrical specifications is written as being quite large. 
 The customer is requesting confirmation of the factors that cause the variation of the Min/Max times of each (Sampling, Conversion) Time. 
 1. Please answer why the variation range is so large. 
 Also, we received other question about whether there is a way to reduce the sampling and conversion time of AD. 2. If you have a solution or a method that you can suggest, please guide us by today. 
 Thank you. 
 Best Regards, 
 David lee.

JimB · Answer

This range of time (min/max) is determined by the ADCLK. For the first line, at 8MHz min ADCLK the time will be the max 5.75us, while the max ADCLK of 40MHz will be the min conversion time of 1.15us. 
 The number ADCLKs required is 46-cycles for the highlighted conversion time, multiply this by used ADCLK. 
 The number of ADCLKs required for the highlighted sample-time is 24-cycles, multiply this by the used ADCLK.