diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index bd2e7ef34b27..da28fdf8756f 100755 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -594,7 +594,7 @@ pinctrl: pin-controller@11030000 { <0 0x110b0020 0 0x04>; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 152>; + gpio-ranges = <&pinctrl 0 0 216>; clocks = <&cpg CPG_MOD R9A07G043F_GPIO_HCLK>; power-domains = <&cpg>; resets = <&cpg R9A07G043F_GPIO_RSTN>, diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi index f5d8bc16c340..cf434de9a4dd 100755 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -386,15 +386,12 @@ sd1_pwr_en { /* Support pinctrl for MMC function of SDHI0*/ sdhi0_pins: sd0 { sd0_data { - pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", - "SD0_DATA3", "SD0_DATA4", "SD0_DATA5", - "SD0_DATA6", "SD0_DATA7"; power-source = <1800>; }; sd0_ctrl { - pins = "SD0_CLK", "SD0_CMD", "SD0_RST#"; power-source = <1800>; + pins = "SD0_CLK", "SD0_RST"; }; }; #else @@ -428,25 +425,23 @@ sd0_ctrl_uhs { sdhi1_pins: sd1 { sd1_data { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; power-source = <3300>; }; sd1_ctrl { - pins = "SD1_CLK", "SD1_CMD"; power-source = <3300>; + pins = "SD1_CLK"; }; }; sdhi1_pins_uhs: sd1_uhs { sd1_data_uhs { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; power-source = <1800>; }; sd1_ctrl_uhs { - pins = "SD1_CLK", "SD1_CMD"; power-source = <1800>; + pins = "SD1_CLK"; }; }; diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4b7d569b3464..515cb1b23b17 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -237,6 +237,58 @@ static const int rzg2ul_pin_info[] = { RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5), }; +static const int rzfive_pin_info[] = { + RZG2L_PIN_INFO(19, 1), + RZG2L_PIN_INFO(20, 0), RZG2L_PIN_INFO(20, 1), RZG2L_PIN_INFO(20, 2), + RZG2L_PIN_INFO(20, 3), RZG2L_PIN_INFO(20, 4), RZG2L_PIN_INFO(20, 5), + RZG2L_PIN_INFO(20, 6), RZG2L_PIN_INFO(20, 7), + RZG2L_PIN_INFO(21, 1), + RZG2L_PIN_INFO(22, 0), RZG2L_PIN_INFO(22, 1), RZG2L_PIN_INFO(22, 2), + RZG2L_PIN_INFO(22, 3), + RZG2L_PIN_INFO(23, 1), RZG2L_PIN_INFO(23, 2), + RZG2L_PIN_INFO(23, 4), RZG2L_PIN_INFO(23, 5), + RZG2L_PIN_INFO(24, 0), RZG2L_PIN_INFO(24, 1), RZG2L_PIN_INFO(24, 2), + RZG2L_PIN_INFO(24, 3), RZG2L_PIN_INFO(24, 4), RZG2L_PIN_INFO(24, 5), + RZG2L_PIN_INFO(25, 1), + RZG2L_PIN_INFO(28, 0), RZG2L_PIN_INFO(28, 1), RZG2L_PIN_INFO(28, 2), + RZG2L_PIN_INFO(28, 3), RZG2L_PIN_INFO(28, 4), RZG2L_PIN_INFO(28, 5), + RZG2L_PIN_INFO(0, 0), RZG2L_PIN_INFO(0, 1), RZG2L_PIN_INFO(0, 2), + RZG2L_PIN_INFO(0, 3), + RZG2L_PIN_INFO(1, 0), RZG2L_PIN_INFO(1, 1), RZG2L_PIN_INFO(1, 2), + RZG2L_PIN_INFO(1, 3), RZG2L_PIN_INFO(1, 4), + RZG2L_PIN_INFO(2, 0), RZG2L_PIN_INFO(2, 1), RZG2L_PIN_INFO(2, 2), + RZG2L_PIN_INFO(2, 3), + RZG2L_PIN_INFO(3, 0), RZG2L_PIN_INFO(3, 1), RZG2L_PIN_INFO(3, 2), + RZG2L_PIN_INFO(3, 3), + RZG2L_PIN_INFO(4, 0), RZG2L_PIN_INFO(4, 1), RZG2L_PIN_INFO(4, 2), + RZG2L_PIN_INFO(4, 3), RZG2L_PIN_INFO(4, 4), RZG2L_PIN_INFO(4, 5), + RZG2L_PIN_INFO(5, 0), RZG2L_PIN_INFO(5, 1), RZG2L_PIN_INFO(5, 2), + RZG2L_PIN_INFO(5, 3), RZG2L_PIN_INFO(5, 4), + RZG2L_PIN_INFO(6, 0), RZG2L_PIN_INFO(6, 1), RZG2L_PIN_INFO(6, 2), + RZG2L_PIN_INFO(6, 3), RZG2L_PIN_INFO(6, 4), + RZG2L_PIN_INFO(7, 0), RZG2L_PIN_INFO(7, 1), RZG2L_PIN_INFO(7, 2), + RZG2L_PIN_INFO(7, 3), RZG2L_PIN_INFO(7, 4), + RZG2L_PIN_INFO(8, 0), RZG2L_PIN_INFO(8, 1), RZG2L_PIN_INFO(8, 2), + RZG2L_PIN_INFO(8, 3), RZG2L_PIN_INFO(8, 4), + RZG2L_PIN_INFO(9, 0), RZG2L_PIN_INFO(9, 1), RZG2L_PIN_INFO(9, 2), + RZG2L_PIN_INFO(9, 3), + RZG2L_PIN_INFO(10, 0), RZG2L_PIN_INFO(10, 1), RZG2L_PIN_INFO(10, 2), + RZG2L_PIN_INFO(10, 3), RZG2L_PIN_INFO(10, 4), + RZG2L_PIN_INFO(11, 0), RZG2L_PIN_INFO(11, 1), RZG2L_PIN_INFO(11, 2), + RZG2L_PIN_INFO(11, 3), + RZG2L_PIN_INFO(12, 0), RZG2L_PIN_INFO(12, 1), + RZG2L_PIN_INFO(13, 0), RZG2L_PIN_INFO(13, 1), RZG2L_PIN_INFO(13, 2), + RZG2L_PIN_INFO(13, 3), RZG2L_PIN_INFO(13, 4), + RZG2L_PIN_INFO(14, 0), RZG2L_PIN_INFO(14, 1), RZG2L_PIN_INFO(14, 2), + RZG2L_PIN_INFO(15, 0), RZG2L_PIN_INFO(15, 1), RZG2L_PIN_INFO(15, 2), + RZG2L_PIN_INFO(15, 3), + RZG2L_PIN_INFO(16, 0), RZG2L_PIN_INFO(16, 1), + RZG2L_PIN_INFO(17, 0), RZG2L_PIN_INFO(17, 1), RZG2L_PIN_INFO(17, 2), + RZG2L_PIN_INFO(17, 3), + RZG2L_PIN_INFO(18, 0), RZG2L_PIN_INFO(18, 1), RZG2L_PIN_INFO(18, 2), + RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5), +}; + struct rzg2l_dedicated_configs { const char *name; u32 config; @@ -1512,6 +1564,36 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; +static const u32 r9a07g043f_gpio_configs[] = { + RZG2L_GPIO_PORT_PACK(3, 0x06, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(8, 0x07, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x08, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x09, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(6, 0x0a, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(6, 0x0b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x0c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), + RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), + RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), + RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +}; + static struct { struct rzg2l_dedicated_configs common[35]; struct rzg2l_dedicated_configs rzg2l_pins[7]; @@ -1598,6 +1680,38 @@ static struct { } }; +//static struct rzg2l_dedicated_configs rzfive_dedicated_pins[15] = { +static struct { + struct rzg2l_dedicated_configs common[15]; +// struct rzfive_dedicated_configs rzg2l_pins[7]; +} rzfive_dedicated_pins = { + .common = { + { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, + (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, + { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, + (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, + { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, + { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, + { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, + { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, + (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, + { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, + { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, + { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, + { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, + { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, + } +}; + static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) { struct device_node *np = pctrl->dev->of_node; @@ -1612,6 +1726,11 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); return ret; } + dev_info(pctrl->dev,"test"); + dev_info(pctrl->dev,"args0: %i",of_args.args[0]); + dev_info(pctrl->dev,"args1: %i",of_args.args[1]); + dev_info(pctrl->dev,"args2: %i",of_args.args[2]); + dev_info(pctrl->dev,"nportpins: %i",pctrl->data->n_port_pins); if (of_args.args[0] != 0 || of_args.args[1] != 0 || of_args.args[2] != pctrl->data->n_port_pins) { @@ -1877,18 +1996,30 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .ngpioints = ARRAY_SIZE(rzg2ul_pin_info), .irq_mask = false, }; - +/* static struct rzg2l_pinctrl_data r9a07g043f_data = { .port_pins = rzg2l_gpio_names, - .port_pin_configs = r9a07g043_gpio_configs, - .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, - .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), - .pin_info = rzg2ul_pin_info, - .ngpioints = ARRAY_SIZE(rzg2ul_pin_info), + .port_pin_configs = r9a07g043f_gpio_configs, + .dedicated_pins = rzfive_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins), + .pin_info = rzfive_pin_info, + .ngpioints = ARRAY_SIZE(rzfive_pin_info), .irq_mask = true, +};*/ + +static struct rzg2l_pinctrl_data r9a07g043f_data = { + .port_pins = rzg2l_gpio_names, + .port_pin_configs = r9a07g043f_gpio_configs, + .dedicated_pins = rzfive_dedicated_pins.common, + .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins.common), + .pin_info = rzfive_pin_info, + .ngpioints = ARRAY_SIZE(rzfive_pin_info), + .irq_mask = true, }; + static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = rzg2l_gpio_configs,