I am designing a data collection system for a piece of industrial equipment. The IDT72V263 looks great for the application but I need to well understand/confirm on a couple of topics
First some details
I plan to use the chip in IDT Standard mode and not FWFT. I don't really see an advantage of FWFT on this application.
The basic plan is to start collecting data on a user command but once a threshold is reached (PAE goes high) the data will be Read Out at the same rate and the Write In clock thus maintaining a set amount of data. Once a trigger is active the Read Out clock will stop and the FIFO should proceed to fill up until FF is reached, This I can capture data before and after the trigger..
Question 1 - Difference between Synchronous or Asynchronus
To my eye I would use synchronous on both the write and read. I am having a bit of an issue understanding how the 2 differ
During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR,the WEN input should be tied to its active state, (LOW).
To my understanding the WR in this mode is essentially the same a the clock and WEN is LOW to write in both.
2 - Details on PAE
I understand that PAE is inverted but I can't find a way to put the bar on top with this editor. Sadly Superline is not available, but I digress
I assume that PAE (PIn 66) should go LOW when the record count goes below the pre-set threshold and will go HIGH if record count increases above it, so writing in or reading out could change it's status accordingly. Is this all correct?
Hi Joe, we don't have FIFO product support on the forums. Can I ask you to put a ticket into myREnesas "my Tickets" ? it will then route directly to the apps engineer for FIFO. Apologies for the inconvenience. BR JE_REN
In synchronous mode, both the write and read operations are controlled by separate clock inputs (WCLK and RCLK, respectively). Data is written into the FIFO on rising edges of the WCLK input, and read out on rising edges of the RCLK input. In synchronous mode, the WEN input is tied to VDD (HIGH) to enable writes.
In asynchronous mode, only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, and the WEN input should be tied to its active state (LOW) to enable writes. Reading data out of the FIFO is still synchronous, and is controlled by the RCLK input.
The advantage of synchronous mode is that it allows for precise timing of the write and read operations, which can be important in certain applications. Asynchronous mode is simpler to implement, but may not be suitable for applications that require precise timing.
PAE (Pin 66) is an active low output that indicates when the FIFO is almost empty (i.e., when the number of words stored in the FIFO falls below a programmable threshold). When the FIFO is almost empty, PAE goes LOW, and remains LOW until the number of words in the FIFO increases above the threshold.
In your application, it sounds like you are using PAE as a trigger to start reading out data from the FIFO once the threshold is reached. When the trigger is active, the Read Out clock will stop, and the FIFO will continue to fill up until it is full. Once the FIFO is full, you can capture data before and after the trigger. HPInstantInk
It is important to note that PAE is an output of the FIFO, and should not be used to directly control any inputs to the FIFO. Instead, it should be monitored by the microcontroller or other external logic to determine when to read out data from the FIFO.