Nearly every embedded system requires that a developer dive into the linker file to parse out space for calibration data, look-up tables or even bootloader and application spaces. Despite modifying the linker file in most applications, developers are generally apprehensive and even intimidated by the linker file contents! All linker files are not created equal and the commands and structure for one compiler will rarely match another’s. Starting in e2 Studio, a linker file configurator is now included to help ease the burden of remembering or investigating how the linker file works. In this post, we will examine how to use the linker file configurator.


Open any Renesas Synergy™ Software project and in the Project Explorer, navigate and expand the scripts folder. Double clicking on the .ld file will open up the linker configurator and result in something similar to the following being displayed.



The linker configurator contains three different tabs:

  • A sections tab for modifying sections and assignments within the linker
  • A memory tab for creating and modifying memory regions such as FLASH, RAM and so forth
  • A plain text view of the linker


First, let’s examine the Sections tab. The sections tab is shown by default when a linker file is double clicked. From a first glance, it can seem a bit overwhelming, but don’t forget there are a lot of default settings already preconfigured and making adjustments to those settings or adding a new section is far easier once you get used to it. For example, let’s say that you want to add a new flash section. Previously this would have required going into the linker file and figuring out where to put it. Now a developer can press the ‘Add Section’ button and configure the section as needed. An example is shown below:


Once the section is created, a developer can click on the section folder on the left side of the configurator and add assignments. Below is an example for creating a new symbol, MyNewSymbol.



The memory tab is perhaps one of my favorites. There are many instances where a developer will want to modify the memory regions defined in a linker. Take for instance, when a developer is creating a bootloader. The developer will need to create separate memory spaces for the bootloader, application space 1 and application space 2. This requires modifying the linker to define where the FLASH memory region begins along with specifying its length. Each application linker file would still only have a single flash region but the region would be a smaller part of the whole. A developer can easily do this by simply changing the start address and length for the memory region. FLASH normally would have started at 0x100000 and had a length of 0x100000. An example for application slot 2 can be seen below where FLASH begins at 0x00180000 and has 0x00100000 for its length.



Using the Sections and Memory configurator is far easier than trying to modify the linker text; However, if you are a developer who is comfortable with the linker file or even prefer the plain text, it’s still possible to access it and modify it manually. This is done by clicking on the tab that has the linker file name. Everything one would expect to see in a linker can then be accessed as shown in the image below.



That’s it! An additional, simply tool to help make changing the linker file easier. In the next post, we’ll pick back up where we left off by examining further how we can debug Synergy based applications.


Until next time,


Live long and profit!





Hot Tip of the Week


Did you know that Renesas provides a set of Technical Updates on all things Synergy? These articles identify newly identified limitations, constraints and other considerations important to development. You can access technical updates from the MCU page, then select the Documentation Tab and click on the Technical Update check box and then the Filter button. For example, you can find S7 related Technical Updates here:


Some example topics are shown below:

Revised information for current version of the User's Manuals

Unexpected GLCD interrupt generated in S7G2 and S5G9 after GLCD starts

Additional description related to the SRAM store buffer  

AES restrictions and changes to orderable part number for S124