ADC unstable meassurements

Dear community,

I am using TB-S1AJ board, and I would like to test how good is the single-ended 16 bits ADC converter from a raw voltage measurement. I am using a simple 100K-100K resistor voltage divisor to test the value from the 2 resistors union point. The voltage measurement should be the half of the Vref. due to the fact I am using the same 3v3 voltage reference.

I know that if we use a high impedance, the measurements may not reach the Vref (Internal 2v5) threshold values due to sample & hold state. To solve this problem, first of all, I reduce the ADCLKD clock to take into account the speed to charge the comparator sample&hold reference voltage, so the internal capacitor has enough time to charge the voltage sample.


To do that I modified internally some of the registers thanks to the aportations of:

My first question would be:

  • Is there a way to make sample&hold time configuration of S1JA configuration inside SSP2v3? – I am getting some errors when I try to use Ch1 in the SSP configuration when I enable Ch1:



On the other hand, the measurements I get changes accordingly to the sample&hold configuration property. If I increase on time, the values reach better the Vref threshold. However, the values oscillate too much or are not stable to apply any kind of control.

My second question would be:

  • Is there a way to make improve the single-ended measurements besides changing the sample&hold and Add/Average count (to 16 measurements mean) properties? – I am getting some errors when I try to use Ch1 in the SSP configuration when I enable Ch1:


I attach the SW I used and the excel with the obtained measurements.

 Best regards,

Parents Reply Children
  • Dear community,

     After some time, the problem of oscillations in the values in counts of the high-precision SAR channels of the uC-S1JA has been understood.

    The problem is due to the high impedance with which the sensor works:

    • If RA, the resistance to adapt the voltage to the input channel, is a very high value, IB will be a very small current value when SWIN_1 closes, the Switch in charge of obtaining the voltage values at a given instant. Therefore, CIN, the internal capacitor of the converter, will take longer to charge. Then, the interpretation of the capacitor charge values can vary. We see these changes in Excel with the calculated values in my question resources.

    In short, there are several solutions. They can be used separately or try to integrate them all. It all depends on the function and architecture of the final application:

    • Increase the S&H times in the ADTRRSx registers so that CIN, the capacitor that internally charges the input voltage values, has more time.
    • Significantly increase AC capacity.Thus, IB is not as dependent on RA and can be loaded much faster. Helping to stabilize the signal. A very high value can alter the ADC response of the channel in use in the transient regime.
    • Reduce the values of RA and RB so that the voltage divider circulates a higher intensity. Thus, when intesity I is very large à IB>, causing the capacitor to charge earlier and the measurements to be more stable.

    I hope it help others...

    Best regards,