Dear community, I am using TB-S1AJ board, and I would like to test how good is the single-ended 16 bits ADC converter from a raw voltage measurement. I am using a simple 100K-100K resistor voltage divisor to test the value from the 2 resistors union point. The voltage measurement should be the half of the Vref. due to the fact I am using the same 3v3 voltage reference.
I know that if we use a high impedance, the measurements may not reach the Vref (Internal 2v5) threshold values due to sample & hold state. To solve this problem, first of all, I reduce the ADCLKD clock to take into account the speed to charge the comparator sample&hold reference voltage, so the internal capacitor has enough time to charge the voltage sample.
To do that I modified internally some of the registers thanks to the aportations of:
My first question would be:
On the other hand, the measurements I get changes accordingly to the sample&hold configuration property. If I increase on time, the values reach better the Vref threshold. However, the values oscillate too much or are not stable to apply any kind of control.
My second question would be:
I attach the SW I used and the excel with the obtained measurements. Best regards,datos.xlsxTB_Blinky_BASIC_CH6_22022_11_11_14h17.zip Juan
After some time, the problem of oscillations in the values in counts of the high-precision SAR channels of the uC-S1JA has been understood.
The problem is due to the high impedance with…