Following  is my query regarding S7G2 ADC. With respect to below Figure , it is observed that the source impedances of the signals are high (in range of 10^5). These signals viz. 1V6DN_VOL, 3V3_VOL, 3V3_A_VOL, 5V_VOL, 10V_VOL, BAT_VOL are to be used as inputs to ADC of processor for monitoring the output voltage of the different supplies. May I know whether such high input impedance to ADC is compatible or do we need to lower the input impedance.




  • Riya,

    If you look at the A/D conversion characteristics in table 59.40 of the S7G2 Hardware Manual (R01UM0001EU0100) you will find the conversion time and other characteristics at different source impedances. For High - precision channels (AN003 - AN006) you should use 300 ohm source impedance if you want to minimize the number of sampling states. In general, the higher the source impedance, the longer it will take to charge the input capacitance of the A/D and you will need more sample states (longer sampling time) to offset this.

  • Thank you Gary. We need to sample the analog signal at a very slow rate of about 1 sample per 5 s. At such slow rate will it cause an issue other than the longer conversion time?
  • Riya -

    When the ADC begins a conversion it must charge the sample capacitor inside the MCU. In the circuit you have shown the charge on the 0.1 uF will transfer to the sample capacitor so that should not be a problem. I would recommend, as Gary indicated, using a longer sample window but I would not expect any issues since the 0.1 uF is many orders of magnitude larger than the sample/hold capacitor in the ADC block
    The key is to ensure that the time between conversions on an input allow the divider to recharge the 0.1 uF capacitor. Since you are sampling the inputs at a slow rate (many seconds) it should not be a problem because the time constants are not that long
    The symptom of too much impedance or too fast a sampling rate is a "noisy" conversion.