How to continuously read eight ADC channels through DMA? Are there any examples available for reading ADCs for RA2A1 and RA4M1?
Please find attached a project written for the RA2A1
It uses DTC block transfer to copy 8 adc results to a buffer, and after 8 sets, the process will repeat.
In the source file hal_enrty.c there is a #define
//#define DTC_CHAIN_FOREVER 1#define DTC_CHAIN_ESCAPE 1
If you select DTC_CHAIN_FOREVER, then the result capture will run forever, with the buffer data being rewritten after 8 sets.
If you select DTC_CHAIN_ESCAPE, then after the number of iterations, set by the #define DTC_WAKE_UP_COUNT, then the ADC interrupt will occur.
Therefore, if you set DTC_WAKE_UP_COUNT to 1, the results buffer will contain 1 set of data.
If you set DTC_WAKE_UP_COUNT to 100, then the result buffer will have been overwritten 100 times and when the adc interrupt occurs, you will have the latest data in the buffer.
The use of the DTC in this block transfer mode does assume that you are using successive ADC channels, for example AN000, 001, 002, 003, 004, 005, 006 & 007. If you were to use no successive channels, for example AN000, AN001, AN002, AN003, AN016, AN017, AN018, AN019 then modifications to the code would be required.
The simplest modification would be to increase you results buffer to be 20 * X elements in size. When the DTC is activated by the ADC scan end interrupt it will read all of the ADC data registers, from AN000 - AN019. As you can see you have wasted buffer space.
There is a more complex version, that uses multiple DTC block transfers that would eliminate the wasted space. However, it does require more set / configuration code. It can be easily done, I just haven't shown it in this example. If however, if it would be of interest I can post another example is required
Hope this is of intereset
Please find attached a new version of the code.
This example scans AN000, AN001, AN002, AN003, AN006, AN007, AN016 and AN018
The data are stored in an array the is x8 deep.
As in the first project the DTC is used in chain mode. However, rater than use a single block mode transfer and using chained transfers to reset the block mode parameters, in this example single channel Repeat Mode transfers are chained together. The advantage of this is that in Repeat Mode, the registers are reset automatically to their is no need to use extra transfers to reset things.
In the same way as before, the process can run forever or can be interrupted by the defines
#define DTC_CHAIN_FOREVER 1
#define DTC_CHAIN_ESCAPE 1
Hope this is of interest