RA2A1 - How to continuously read eight ADC channels through DMA?

How to continuously read eight ADC channels through DMA? Are there any examples available for reading ADCs for RA2A1 and RA4M1? 

  • Yes, examples exist.
    However, which example to share requires on your requirements.
    You wish to read 8 channels.
    Are you storing these data in RAM? How large is your results buffer? Are you wishing to store just 1 * 8 results and then overwrite these data, or do you wish to store X * 8 results before you overwrite the data.
  • I thought of using sort of a 8 * 8 buffer to store 8 consecutive results from each of 8 channels and then to calculate an average value for each channel. Values would be overwritten by newer ones as they come. Unless there is a better way to do it.
  • EK_RA2A1_ADC_DTC.zip

    Please find attached a project written for the RA2A1

    It uses DTC block transfer to copy 8 adc results to a buffer, and after 8 sets, the process will repeat.

    In the source file hal_enrty.c there is a #define 

    //#define DTC_CHAIN_FOREVER   1
    #define DTC_CHAIN_ESCAPE  1

    If you select DTC_CHAIN_FOREVER, then the result capture will run forever, with the buffer data being rewritten after 8 sets.

    If you select DTC_CHAIN_ESCAPE, then after the number of iterations, set by the #define DTC_WAKE_UP_COUNT, then the ADC interrupt will occur.

    Therefore, if you set DTC_WAKE_UP_COUNT  to 1, the results buffer will contain 1 set of data.

    If you set DTC_WAKE_UP_COUNT  to 100, then the result buffer will have been overwritten 100 times and when the adc interrupt occurs, you will have the latest data in the buffer.

    The use of the DTC in this block transfer mode does assume that you are using successive ADC channels, for example AN000, 001, 002, 003, 004, 005, 006 & 007.  If you were to use no successive channels, for example AN000, AN001, AN002, AN003, AN016, AN017, AN018, AN019 then modifications to the code would be required.

    The simplest modification would be to increase you results buffer to be 20 * X elements in size.  When the DTC is activated by the ADC scan end interrupt it will read all of the ADC data registers, from AN000 - AN019.  As you can see you have wasted  buffer space.

    There is a more complex version, that uses multiple DTC block transfers that would eliminate the wasted space.  However, it does require more set / configuration code.  It can be easily done, I just haven't shown it in this example.  If however, if it would be of interest I can post another example is required


    Hope this is of intereset



  • Dear Richard,

    I am interested to see the other example as well.

    Best Regards
  • Sorry, didn't have a chance to upload an example today.
    Should be able to do it tomorrow.

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