DMA access using SCI.UART in RA4M1 series controller.

Hello viswa,

EK_RA6M2_SCI_DMAC.zip

Please find attached a project that shows how to use the DMAC with UART.  (FSP1.3.0, e2studio 2020-07)

Please note that this is written and tested for a RA6M2 device as I do not have immediate access to a RA4M1.  However, you will be able to port this over.

As Warren mentioned in an earlier post, the DMA is not directly supported when you add a UART stack; on the DTC is.

However, it is possible by adding additional DMAC transfer drivers.

In this example I use the DMA to perform data transmission and reception

Configure the DMA transfer drivers are required, for example:

When you run the code, the data string "Test Data String" will be transmitted twice.  The first time is via the CPU and interrupts, the second time is via the DMAC and interrupts.

The key to getting the DMA to trigger is to disable the interrupts in the ICU interrupt enable register.  If you do not do this then their is contention between the CPU and the DMA, and you do not get the behviour you expect.

I hope the code and comments in hal_entry.c explain this.

Regards, Richard

hal_entry.zipThanks for the help Richard. It worked for me. But i couldn't controll the flow. The last Dma request I place will overwrite the previous request. If I put a breakpoint between those requests then I can see the Whole transmitted message.

I have these problems,

1. After using these lines, DMA starts working but how to get UART back in control.

  " R_ICU->IELSR[SCI0_RXI_IRQn] = 0U;

    R_ICU->IELSR[SCI0_TXI_IRQn] = 0U; "

2. How to ensure all data is transfered without using fifo.

3.Datasheet mentions to clear IR flag, instead we are clearing all the IELSR register, why?

4."  When using DMAC or DTC, be sure to write transmit data to TDR or TDRHL in the SCIn_TXI interrupt request handling routine. "its mentioned in datasheet. SCIn_TXI ISR routine is one time operation isnt it? Just before DMA takes over?. Please find the code attached .

hal_entry.zipThanks for the help Richard. It worked for me. But i couldn't controll the flow. The last Dma request I place will overwrite the previous request. If I put a breakpoint between those requests then I can see the Whole transmitted message.

I have these problems,

1. After using these lines, DMA starts working but how to get UART back in control.

  " R_ICU->IELSR[SCI0_RXI_IRQn] = 0U;

    R_ICU->IELSR[SCI0_TXI_IRQn] = 0U; "

2. How to ensure all data is transfered without using fifo.

3.Datasheet mentions to clear IR flag, instead we are clearing all the IELSR register, why?

4."  When using DMAC or DTC, be sure to write transmit data to TDR or TDRHL in the SCIn_TXI interrupt request handling routine. "its mentioned in datasheet. SCIn_TXI ISR routine is one time operation isnt it? Just before DMA takes over?. Please find the code attached .

Hi,

Please look at the attached project.

EK_RA4M1_SCI_DMAC.zip

When the DMAC has finished writing data to the TDR, the DMAC end interrupt will trigger.

I use this interrupt to enable the TEIE (transmit end interrupt)

This interrupt will trigger when data transmission has completed and the TSR is empty.

At this point, the SCI UART callback is called.

In this callback I set a flag.

At this point I reconfigure the DMAC and send more data.

With this config, in my tests, there is no data corruption

Please try this

Regards,

Richard

Hi,

Please find attached an update.

3482.EK_RA4M1_SCI_DMAC.zip

This project will address the issue of not being able to switch between using the DMAC and CPU.

You will see in the while(1) loop, the application will send 10 continuous data strings (on SCI0) via DMAC and then via the CPU.

This process is repeated every time you press the SW1 button on the EK-RA4M1 board

You will see that when a switch between DMAC and CPU is required (and vice-versa) we have to set / clear the IELSR (ICU Event Link Setting Register) and DELSR (DMAC Event Link Setting Register) accordingly

Hope this helps

Regards,

Richard