SPI Slave, Chip Select Issue

Hi Nasrulla,

Thanks for reaching out to Renesas Engineering Community.

What is your value for 'length' in R_SPI_Write ?

Regards

Hi Nasrulla,

Is there any update on this issue ?

Thanks and regards

Facing same issue Please go thorough the updated code.

it is 6 Bytes

Hello,

Can you try the following code for the SPI write function ?

err = R_SPI_Write (&g_spi0_ctrl, txbuf,  WRITE_TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
assert(FSP_SUCCESS == err);
    
while (false == g_transfer_complete)
{
    ;
}

g_transfer_complete = false;

Also, in your code txbuf is filled with 0's, is that by design ?

Regards

Hello ,

Could you please send us also a screenshot of your FSP Configuration settings in e2studio? Also what does API  R_SPI_Write() returns to you and what value does g_transfer_complete gets does it enter your callback function?

Thank you!

Best Regards,

IK_Renesas

Hello again,

Please notice that there is also a limitation in the module when setting slave mode. This limitation has to do with Clock Phase settings. When setting clock phase  CPHA= 0, which means data sampling on even edge, data variation on odd edge and you want to configure RA MCU to slave mode, the master must toggle the SSL pin after every data frame (Even if the device supports SSL Level Keeping). Because of this hardware limitation, the module will return FSP_ERR_UNSUPPORTED when it is configured to use CPHA=0 setting in slave mode.

Also notice that RA2L1 does not support SSL Level Keeping.

For more details about r_spi module check the documentation here:

https://renesas.github.io/fsp/group___s_p_i.html#ga97b928cbe1a9df78d4ab5ff69732dbcd

Best Regards,

IK_Renesas

Hi IK_Renesas,

Thanks for the input. I did figured out with multiple Iterations, if CPHA == 1 then there is no issu in chip select. But when keeping CPHA == 0 Chip select toggle is required for each byte.

I was little confuse with the Datasheet, in CPHA description. 

In RASC I have kept data Sampling on Even Edge, During Debug I could read CPHA = 1, Please find the below screen shot of registers

Now the confusion is CPHA  = 1 is Data Sampling at Even Edge, and CPHA = 0 Means Data Sampling at Odd Edge. 

Please let me know. Is the correction needed in Datasheet or in RASC Configuration. Or anything I am missing.

Apologies for the delay. I think the confusion is because the are 2 different terms for the same thing. In short: 

even edge = trailing edge 

odd edge = leading edge

The first edge of the clock in the transfer period (rising or falling) is assumed to be a leading/odd edge (or edge number 1) and then the trailing/even (edge number 2) follows.

When CPHA = 0 the sampling occurs at odd/leading edge:

When CPHA = 1 the sampling occurs at even/trailing edge:

I hope it clears up.

Thank you for your response. We also figured out the same using trial and error.

In Leading/Odd Edge when CPHA = 0

we are facing issue.

Renesas is Kept at in Slave mode.

rSpi_read() works fine without any issues.

rspi_write() has some issues. For Every 6 Bytes successful transfer we need to toggle chip select in Master for 6 times.

If we toggle chip select only one time for a 6 byte frame. Then we receive only first byte, all other are zero.