I require some direction on understanding the SPI Mode of operation in Renesas Controller. Since we are facing some issues as listed below.
#define READ_TRANSFER_SIZE 6#define WRITE_TRANSFER_SIZE 6
uint8_t txbuf[6] = {0};
uint8_t rxbuf[6] = {0x4, 0x5, 0x6, 0x7, 0x8, 0x9};
/* R_SPI_READ is working */
// Read 6 Bytes of SPI Command From Hosterr = R_SPI_Read(&g_spi0_ctrl, rxbuf, READ_TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);if((err == FSP_SUCCESS) && (g_transfer_complete == true)){ g_transfer_complete = false;}
/* Below Operation Sends only 1 Byte when chip select changed high to low rather sendong 6 Bytes */
/* send next 6 bytes to MISO */ /* Send Feed back Data to Master Controller */err = R_SPI_Write (&g_spi0_ctrl, txbuf, WRITE_TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);if((err == FSP_SUCCESS) && (g_transfer_complete == true)){ g_transfer_complete = false;}
Hello again,
Please notice that there is also a limitation in the module when setting slave mode. This limitation has to do with Clock Phase settings. When setting clock phase CPHA= 0, which means data…
It depends on the bit width you have set to your operation. In your case bit width is set to SPI_BIT_WIDTH_8_BITS, which is one byte.
From your code:
err = R_SPI_Write (&g_spi0_ctrl, txbuf, WRITE_TRANSFER_SIZE…
Hi Nasrulla,
Thanks for reaching out to Renesas Engineering Community.
What is your value for 'length' in R_SPI_Write ?
Regards
it is 6 Bytes
Hi IK_Renesas,
Thanks for the input. I did figured out with multiple Iterations, if CPHA == 1 then there is no issu in chip select. But when keeping CPHA == 0 Chip select toggle is required for each byte.
I was little confuse with the Datasheet, in CPHA description.
In RASC I have kept data Sampling on Even Edge, During Debug I could read CPHA = 1, Please find the below screen shot of registers
Now the confusion is CPHA = 1 is Data Sampling at Even Edge, and CPHA = 0 Means Data Sampling at Odd Edge.
Please let me know. Is the correction needed in Datasheet or in RASC Configuration. Or anything I am missing.
Apologies for the delay. I think the confusion is because the are 2 different terms for the same thing. In short:
even edge = trailing edge
odd edge = leading edge
The first edge of the clock in the transfer period (rising or falling) is assumed to be a leading/odd edge (or edge number 1) and then the trailing/even (edge number 2) follows.
When CPHA = 0 the sampling occurs at odd/leading edge:
When CPHA = 1 the sampling occurs at even/trailing edge:
I hope it clears up.
Thank you for your response. We also figured out the same using trial and error.
In Leading/Odd Edge when CPHA = 0
we are facing issue.
Renesas is Kept at in Slave mode.
rSpi_read() works fine without any issues.
rspi_write() has some issues. For Every 6 Bytes successful transfer we need to toggle chip select in Master for 6 times.
If we toggle chip select only one time for a 6 byte frame. Then we receive only first byte, all other are zero.
Hello,
Could you please repost your configuration, since we are not able to see the pictures of the analyzer you've sent.
Thank you!
Best Regards,
IK
In Mode 0, CPHA = 0, Leading edge, R_SPI_Write to transfer 6 Bytes data at a time.
Below Figure - Chip Select Toggle Once 6 Byte - Not working only 1st Byte is received All others 0.
Below Figure - Chip Select Toggle on every Byte - Working All 6 Bytes received.
So as far I can understand when setting CPHA = 0 and toggle chip select on every byte you are able to transmit the desired number of bytes, whereas keeping chip select low for 6 bytes, with the same settings results transmitting only one byte of total 6 bytes you want to transmit. Am I correct?
BR
Hi,
Yes you are right.
Since you are using r_spi module , you have set CPHA = 0 and configured RA2L1 as slave , this is a normal behavior since you must toggle chip select for every byte. This is a limitation of r_spi module as I mentioned in my previous answer. Take a look in the picture please. This is a hardware limitation.
Thanks for the Response.
I assumed word "frame" could be of any size. Now I understood frame is of 1 Byte.
err = R_SPI_Write (&g_spi0_ctrl, txbuf, WRITE_TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
Hope it helps!