Is hardware enabled DMA ping pong possible in RA6M3 ?

Hi all,

I want to know if it is possible to have a DMA which can give an interrupt at the middle and at the end and rolls over without blocking.

I have so far not been able to find this in hardware manual. All the possible solution involves DMA ISR and changing destination in it. My problem is the system is running threadx and because of that interrupt service latency is unacceptably huge and unpredictable. In this circumstances if system waste time waiting for ISR to update the DMA destination address is catastrophic.

And I am pretty sure Renesas MCUs don't have this feature yet, I hope they will include this in the future product and also ADC should have ring buffer.


Thanks

Parents
  • Hello,

    Thanks for reaching out Renesas Engineering Community?

    Have you read the documentation of r_dmac module? It is possible to trigger an interrupt after each transfer or after the last transfer.

    Take a look please in the link below:

    https://renesas.github.io/fsp/group___d_m_a_c.html

    Thank you!

    Best Regards,

    IK

  • ISR triggered after each transfer is useless, I want DMA to give interrupt let's say half way and keep going and give another at halfway and give another at the end and roll over. Is this possible ? I don't think so.

    And yes, I have gone through all the documentation and didn't find anything . Thanks for reply.

  • There are 2 options for a DMA interrupt generation:

    • Interrupt after all transfers have completed
    • Interrupt after each block, or repeat size is transfered
  • The issue is DMA is not 'rolling over' , you have to serve interrupt and enable DMA again. I want to see if DMA rolls over automatically .

    Let's imagine I have data generated at location 0xDEADBEEF every 10 us and I want to use DMA to write it in buffer

    uint8_t buf [1024];

    Now set DMA source 0xDEADBEEF and destination 'buf'

    data size 1 byte

    Now I want to repeat destination area infinitely (Not possible in Renesas)

    Also I want  to have interrupt saying that half buffer is full but at the same time I do not want to block DMA transfer( DMA should proceed to fill buf[512] even if ISR at buf[511] is not served) [this is not possible in Renesas]

    Also at the interrupt buf[1023] DMA should give me interrupt and roll over to buf[0]


    This is I call ping pong DMA , is this possible ?

    This way I do not miss any data generated at each 10 us and if I have sufficiently big enough buffer I have some time to process buffer as well.

    The issue is , DMA is occupied while interrupts are generated and served and it is amounting in losing data. Because in some systems interrupt latency is more than 10 us. see this issue.

    community.renesas.com/.../adc-conversion-time-varies-unexpectedly-for-single-channel

  • If you use DMA repeat mode, e.g. on a 1024 buffer, it will continuously write to that buffer, i.e. achieving the roll-over fil_buf[1023] to fil_buf[0]. At rollover you get a dma interrupt.  DMA continue to operate while you are in the ISR.  For the interrupt in the middle, you need to start a one shot timer for 512-buffer time while you are in the dma end interrupt. 

    Unfortunately you can only repeat 65536 times. Then you have to re-start the DMA.

  • @CS Yep

    you need to start a one shot timer for 512-buffer time while you are in the dma end interrupt. 

    For this to work, DMA trigger should also be the count up source of Timer, right ? If the DMA trigger can not be the count up/down source than this approach will not work , right ? 

  • The DMA can be triggered by ADC conversion completion.  The DMA continues operation while you are processing dma end int and later the timer int.

  • I was asking about Timer interrupt. Timer also counts the instances of DMA transfer, and to do that timer needs to get triggered for up\down counting. So If the event can not be timer up\down count source, we can not have interrupt in the middle ? 

  • You try to use 512 buffer time.  If your adc has high jitter, maybe you set (512+alpha). By the time it is up, you should have valid data  0..511 in your buffer. It is not exactly in the middle, maybe pass the middle. Maybe that will work?

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