Is hardware enabled DMA ping pong possible in RA6M3 ?

Hi all,

I want to know if it is possible to have a DMA which can give an interrupt at the middle and at the end and rolls over without blocking.

I have so far not been able to find this in hardware manual. All the possible solution involves DMA ISR and changing destination in it. My problem is the system is running threadx and because of that interrupt service latency is unacceptably huge and unpredictable. In this circumstances if system waste time waiting for ISR to update the DMA destination address is catastrophic.

And I am pretty sure Renesas MCUs don't have this feature yet, I hope they will include this in the future product and also ADC should have ring buffer.