How to Read/Write to 24LC512 EEPROM using either R_IIC_MASTER or R_SCI_I2C drivers

Hi Marek,

You can set the slave address on FSP configurator:

Otherwise you can change the slave address in runtime using R_IIC_MASTER_SlaveAddressSet or R_SCI_I2C_SlaveAddressSet.

The simple examples on https://renesas.github.io/fsp/group___i_i_c___m_a_s_t_e_r.html and https://renesas.github.io/fsp/group___s_c_i___i2_c.html might be useful.

Please let us know if you have more question on this issue.

Regards

Thank you for pointing me in the right direction. 

I have few more questions.

Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. I would like to use this feature to maximize bus throughput. How can I realize ACK polling? (Sending Start condition followed by the control byte). Would I just use R_IIC_MASTER_Write() command with NULL and zero bytes length for this? How to detect that ACK was not returned from slave?

Marek said:

Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete

The ACK bit is returned in every write command:

If a NACK is returned, the error interrupt (EEI) will be triggered and callback function will be entered.

I am having troubles with the callback function. The callback arguments have a pointer to p_context and the event enum of the i2c_master_event type that has only three possible values 

I2C_MASTER_EVENT_ABORTED

I2C_MASTER_EVENT_RX_COMPLETE

I2C_MASTER_EVENT_TX_COMPLETE

How can I add NACK triggering to the callback function?

Also, sometimes I do not get the TX_COMPLETE interrupt, from R_IIC_MASTER_Write() what might be the reason?

The callback function will be triggered with a I2C_MASTER_EVENT_ABORTED event under the following conditions:

So if a NACK is receiver, the callback function will be triggered automatically.

Marek said:

Also, sometimes I do not get the TX_COMPLETE interrupt, from R_IIC_MASTER_Write() what might be the reason?

If a TX_COMPLETE is not returned, it is possible that an error occurred.

Indeed, this part has 5ms Write Cycle Time, so there was not enough wait time between read and writes. As soon as I added 5ms wait it works every time.

It seems that checking for NACK makes sense. I am not sure how to distinguish between Start, Stop, and NACK conditions if all of them are triggered with the I2C_MASTER_EVENT_ABORTED event.

Indeed, this part has 5ms Write Cycle Time, so there was not enough wait time between read and writes. As soon as I added 5ms wait it works every time.

It seems that checking for NACK makes sense. I am not sure how to distinguish between Start, Stop, and NACK conditions if all of them are triggered with the I2C_MASTER_EVENT_ABORTED event.

If you want to enable only NACK as error interrupt condition, it would be easy - just set NAKIE = 1 and others to 0.

Otherwise you can check if NACKF = 1:

Can I do this through FSP? It sounds like I need to go deep into low-level by setting the hardware registers directly.

If an error occurs, the event I2C_MASTER_EVENT_ABORTED will be returned. But if there are more than one sources that can cause an error, you will need to check some registers to determine that it was actually the NACK.

By default TMOIE, ALIE, NAKIE, RIE and TIE are all enabled and rest disabled.