Hello, @supporter.
I am working on an RA6M3G device.
I tried to erase the chip using J-Flash Lite V7.92c but was unsuccessful.
I used Jlink Commander V7.92c but still failed.
Here log:
SEGGER J-Link Commander V7.92c (Compiled Aug 30 2023 15:00:03) DLL version V7.92c, compiled Aug 30 2023 14:58:23 Connecting to J-Link via USB...O.K. Firmware: J-Link OB-S124 compiled Jun 20 2023 17:09:11 Hardware version: V1.00 J-Link uptime (since boot): 0d 00h 06m 55s S/N: 831334275 USB speed mode: Full speed (12 MBit/s) VTref=3.300V Type "connect" to establish a target connection, '?' for help J-Link>connect Please specify device / core. <Default>: R7FA6M3AH Type '?' for selection dialog Device> Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. <Default>: 4000 kHz Speed> Device "R7FA6M3AH" selected. Connecting to target via SWD InitTarget() start Identifying target device... SWD selected. Executing JTAG -> SWD switching sequence... Initializing DAP... DAP initialized successfully. InitTarget() end - Took 11.2ms Found SW-DP with ID 0x5BA02477 DPIDR: 0x5BA02477 CoreSight SoC-400 or earlier Scanning AP map to find all available APs AP[2]: Stopped AP scan as end of AP map has been reached AP[0]: AHB-AP (IDR: 0x24770011) AP[1]: APB-AP (IDR: 0x44770002) Iterating through AP map to find AHB-AP to use AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410FC241. Implementer code: 0x41 (ARM) Found Cortex-M4 r0p1, Little endian. FPUnit: 6 code (BP) slots and 2 literal slots CoreSight components: ROMTbl[0] @ E00FF000 [0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7 [0][1]: E0001000 CID B105E00D PID 003BB002 DWT [0][2]: E0002000 CID B105E00D PID 002BB003 FPB [0][3]: E0000000 CID B105E00D PID 003BB001 ITM [0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU [0][5]: E0041000 CID B105900D PID 000BB925 ETM [0][6]: E0042000 CID B105900D PID 002BB908 CSTF [0][7]: E0043000 CID B105900D PID 001BB961 TMC [0][8]: E0044000 CID B105F00D PID 001BB101 TSG Memory zones: Zone: "Default" Description: Default access mode Cortex-M4 identified. J-Link>erase No address range specified, 'Erase Chip' will be executed 'erase': Performing implicit reset & halt of MCU. Reset: Halt core after reset via DEMCR.VC_CORERESET. Reset: Reset device via AIRCR.SYSRESETREQ. T-bit of XPSR is 0 but should be 1. Changed to 1. T-bit of XPSR is 0 but should be 1. Changed to 1. Erasing device... J-Link: Flash download: Only internal flash banks will be erased. To enable erasing of other flash banks like QSPI or CFI, it needs to be enabled via "exec EnableEraseAllFlashBanks" ****** Error: Timeout while erasing sectors, RAMCode did not respond in time (PC = 0x1FFE040A, XPSR = 0x41000000, SP = 0x1FFE08C0)! Failed to erase sectors. J-Link: Flash download: Total time needed: 10.220s (Prepare: 0.161s, Compare: 0.000s, Erase: 10.006s, Program: 0.000s, Verify: 0.000s, Restore: 0.052s) ERROR: Erase returned with error code -5. J-Link>
Could you please help me check it and give me the solution?
Thank you.
Hello quanvo,
Thanks for reaching out Renesas Community.
Can you try to initialize device back to factory default using Renesas Devision Partition Manager through e2studio, take a look below:
Please…