Hi,
does the RA6M5 I2C master IP support clock stretching? I don't find this feature mentioned in the hardware user manual.
If not, is there an existing RA MCU supports this feature in I2C master IP? I've browsed a few RA MCUs (e.g. RA4M1) but I could not find this. The only place I found is in RA8M1, that clock streching is supported by I3C interface when working in I2C mode.
Thanks!
Hello,
Clock stretching is used by a I2C slave device to keep the SCL line low and have more time to handle data or prepare a response for the master device. It is not normally used by I2C master device.
FSP supports clock stretching on I2C slave modules.
thanks for the quick response.
My understanding for clock streching on master side is that, when slave is streching the clock (holding clock line low), the master could:
- wait until it can drive to expected state, so further clocks are merely delayed. This is successful support of clock streching on master side.
- drive the SCL line without monitoring the state. This may end up in a NACK, as the slave will unlikely ack the 9th clock (the clock would not be really created on the bus). This is a failure of supporting clock streching on master side.
- Drive the SCL line and monitor the state, and raise error as it cannot drive it to expected HIGH. This is another form of faling to support clock stretching.