UART FIFO How does it work?

Question

Hello, 
 I am trying to understand the workings of the FIFO. Reading the Manual has left some question marks and the FSP documentation is no help. 
 I am refering to this example flow chart:

As I understand the FIFO buffer, it is possible to store up to 16 bytes in a fifo register. 
 It is possible to configure a trigger, which indicates when a certain amount of data is in the buffer. 
 When triggered, Data is read in SCI_nRXI but only as long as it does not fall under a certain threshold FCR.RTRG 
 After Reading Data until threshold is hit, it is somehow decided if all data is received. 
 
 My questions: 
 One: 
 In Step 5: What is the condition that all data is received? Is it the amount of data I as a user am specifiying in the fsp read routine RM_COMMS_UART_Read? 
 Two: 
 Do I understand it correct, that if the fifo trigger occurs,the amount of data read is [amount above +1]? For example the trigger value is 4. When 4 bytes are in the fifo -> trigger -> 1 byte read -> continue? 
 Three: 
 From the FSP documentation: 
 
 Only if the trigger is set to 15 bytes the timeout is implemented? There is no timeout when setting the trigger to another value? This confuses me because the manual states this: 
 
 From my understanding the timeout is always set. 
 Four: 
 Can you point me to an example or use-case where a FIFO buffer would be useful? 
 Thank you in advance for your time and effort 
 Best Regards Joe

AZ_Renesas · Accepted Answer

The flow chart's step 4 refers to receiving data in the SCIn_RXI interrupt handling routine. The SCIn_RXI interrupt will be triggered while the number of data is FIFO is above the RTRG value. The software is allowed to read as many data as it wants from FIFO. 
 Regarding the timeout of 15 ETUs: 
 
 The rm_comms_uart callback function will return an event based on the r_sci_uart event. A look on the source code of rm_comms_uart_callback in rm_comms_uart.c may be helpful. 
 If the timeout triggers an error event, the rm_comms_uart will return with a RM_COMMS_EVENT_ERROR eventually.

AZ_Renesas · Answer

Hello, 
 Apologies for the delay. 
 1) The condition for all data reception is the even RM_COMMS_EVENT_RX_OPERATION_COMPLETE. This event is returned by the callback function when the amount of data specified in RM_COMMS_UART_Read is received. You can check the Basic Example on FSP documentation for this implementation. 
 https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___u_a_r_t.html 
 2) Not sure what you mean. When the amount of receive data in FRDRHL (FIFO) is equal to or greater than the receive triggering number the interrupt occurs and software can read data from FIFO. There is no limitation on how many bytes will be read. 
 3) The SSR_FIFO.DR bit is set to 1 for any specified receive triggering value - not only 15. 
 FIFO can be useful when less interrupt handling is necessary. Also if you do not read a byte in time, the next byte will overwrite it. This can be avoided with FIFO.

UART FIFO How does it work?

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