Hi,
I am working with a RA6M3 device. I am using the device in master mode to collect the data from slave continuously after setting up the slave. Below is my code to read data without using the API functions. I am able to generate the clock and get data into my DMA buffer. But, my SPI generates uneven no of clock pulses for data reception upon the data ready interrupt from slave. I should read 4 bytes of data, but sometimes read 5-6 bytes or only 1 byte. Could anyone guide me on this. I have shared the configuration and code below.
Regards,
Lumi
Hello Lumi,
Thanks for reaching out Renesas Engineering Community!
Would it be possible to share with me the whole configuration.xml file in order to be able to check also the r_dmac stacks properties?
Also please check the private message I have sent to you.
Best Regards,
IK_Renesas
Hi,I have shared the project file.Regards,
Lohitha
After checking your settings and the DS of the ADC you are using the specific ADC seems to support SPI mode3.
Which means that the Clock Polarity should be set to CPOL=1 SCKL is idle when high and the regarding the phase CPHA=1 which means that the data are sampled when the clock goes to it's idle voltage level.
Please check if this apply in your application? Are the data sampled when the clock goes high (idle state) for the specific polarity?
Also have you tried to set a lower bitrate to see how the device operates?
A screenshot from a logic analyzer also showing exactly the case that the issue occurs would help a lot.
Thank you.
IK
Hi,I have already setup my SPI in Mode 3 with clock idle high and it is sampling based on the ADC specs. It is the same scenario with lower bitrate (also tried the higher bitrate). Below are the screenshots and logic analyzer snaps. It works fine with the use of API functions but manually setting up SPI gives incorrect no of bytes.
Hello Lohitha,
Unfortunattely I do not have the specific ADC to test exactly your project.
But after checking your project in detail. I can find one obvious mistake.
For configuring the DMA transfer for receive you are using the SPI_RXI (receive full interrupt) as activation source.
However as mentioned in the HW manual of RA6M3:
It is prohibited to set the same peripheral event as CPU interrupt and also at the same time using it to trigger the DMA transfer.
When debugging your project I see that this event is written in the R_ICU->IELSR[0] register.
And this event is also set in the DELSRn register for DMA channel 1 which is used for receive transfer.
As soon as the R_DMAC_Open() API is called the activation source to trigger the DMA is set to this event.
However as already mentioned this is prohibited.
So please make sure that before configuring the DMA channel 1 for receive this event is not also configured as a CPU interrupt on the IELSR register.
So in your case please make sure that you disable this event in the ICU and the NVIC, by typing in your code:
R_ICU->IELSR[0] = 0;
To make sure this event is not used also from the ICU and the NVIC but only is used to trigger your DMA transfer.
I am happy to say that I have resolved this issue. Thank you for the response.Regards,