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Renesas RA8D1 evaluation kit MIPI DSI

Student01HF

Hello,

We are trying to use a 1280X1024 Dual LVDS display that is connected via a MIPI -> Dual LVDS converter.

The converter requires that we use a continuous DSI CLOCK in HS mode and at least one DSI Data lane which can switch between HS and LP mode, we have looked at the User manual: Hardware for the RA8D1 processor and the FSP documentation for the MIPI DSI.

Could anyone clarify the following:

  1. The MIPI PHY section of the User Manual mentions two MIPI DSI "Operation Channels" and it also mentions that these cannot be used simultaneously. This is very important because later on the datasheet mentions the following:
    Channel-0 supports only LP mode (LP-TX, LP-RX), while Channel-1 supports LP mode (LP-TX, LP-RX) and HS mode
    (HS-TX). There are 8 descriptors for each channel.
    In our case, it seems we cannot use channel-0 because we need both LP and HS mode.

    How do we select which channel to use?
  2. The MIPI PHY Interface FSP package documentation (https://renesas.github.io/fsp/group___m_i_p_i___d_s_i.html) also says: Two internal channels may be used for command mode operations, available for all physical lane configurations. Channel-0 supports only LP mode (LP-TX, LP-RX), while Channel-1 supports LP mode (LP-TX, LP-RX) and HS mode (HS-TX).

    Aside from that however it also mentions the following (which we have not found back in the User Manual):
    Communication to the external display occurs via one or more data lanes and one clock lane. Each of these lanes has dedicated pins. Lane 0 is capable of low-power data transfer and bidirectional communication with a display. Lane 1 is capable of low-power or high-speed data transfer to the external display.

    If this is correct, then that means only lane 1 may be used for driving our display. However the User Manual only mentions that only lane 0 is capable of bidirectional LP mode. That does not mean that lane 0 is NOT capable of both HS and LP.

    Does lane 0 support both HS and LP modes?
  3. The converter requires a DSI CLOCK of +/- 480 MHz, I believe the MIPI PHY is more than capable of outputting this..
    How do we set the DSI OUTPUT CLOCK frequency?

Kind regards



Added third question
[edited by: Student01HF at 6:36 (GMT 0) on 13 Aug 2024]
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  • 0

    Hi,

    We have received your request and will give you a reply ASAP.

    BR,

    NP_Renesas

  • 0 in reply to NP_Renesas

    Hi,

    Please take note of the recommended maximum resolution for the GLCDC (given they are talking about using a 1280x1024 LCD panel) :- ** 

    RA Flexible Software Package Documentation: Graphics LCD (r_glcdc) (renesas.github.io)

     

    the figures for the RA8 will be based on 32 bit SDRAM, the EK-RA8D1 only has 16-bit SDRAM fitted.

     

    How do we select which channel to use?

    Don't confuse the Command Mode Operation Channels and the Virtual Channel set in the DSI Command Packet.

    To choose which Command mode Operation channel to use, write to the registers for the required Command Mode Operation Channel (n= 0 or 1), e.g. :- 

     

    To set the Virtual Channel sent in the DSI Command Packet , this is set in the SQCHnDSCmAR : Sequence Channel n Descriptor-m A Register :- 

    The sequence channel registers are used by the R_MIPI_DSI_Command() API RA Flexible Software Package Documentation: MIPI Display Serial Interface (r_mipi_dsi) (renesas.github.io)

    the virtual channel for the command packet is set in the message structure passed to  R_MIPI_DSI_Command( ) :- 


    There is a known issue with the R_MIPI_DSI_Command( ) API :- 

    Issue

    Transmission of images is not affected

    1. Transmission of LP asynchronous messages - sent via R_MIPI_DSI_Command - will only output when the command channel is set to virtual channel (VC) 0.
    2. Transmission of HS asynchronous messages- sent via R_MIPI_DSI_Command - will only output when the command channel is set to VC 1.

    Note: This means that LP commands will be received only by displays configured as VC 0 (the most common configuration) and HS commands will be received only by displays configured as VC 1.

    Workaround

    This issue does not affect situations where exclusively LP asynchronous commands are sent to a display controller configured for use of virtual channel 0 (this is common). Similarly, this issue would not affect configurations where exclusively HS asynchronous commands are sent to a display controller that uses virtual channel 1 (not common). For other configurations, there is no workaround at this time.

    Affects versions:
    v5.0.0
    v5.0.1
    v5.1.0
    v5.2.0
    v5.3.0
    v5.4.0

     

    Does lane 0 support both HS and LP modes?

    Yes.

     

    How do we set the DSI OUTPUT CLOCK frequency?

    Looks like the DSI clock output frequency is DSI PLL Frequency / 2, you can set the DSI PLL Frequency in the properties of the r_mipi_phy driver.

    BR,

    NP_Renesas

  • 0 in reply to NP_Renesas

    Hello,

    Thanks for the reply. At least now the DSI CLOCK output frequency is correct.

    The issue mentioned does not affect "transmission of images", what does that mean? Is the buffer from the GLCDC driver considered an image?

    The datasheet for the converter mentions the following:

    It seems I need to be able to transition my data lanes from HS to LP and back. Is this part of the regular MIPI DSI spec already? Or simply not supported now because of the issue mentioned above.

    Perhaps this snippet from the datasheet clarifies things:



    To clarify, the converter we use does NOT support any commands from MIPI, just data which is later converted to a dual LVDS signal. This is the specific converter we use: https://www.ti.com/product/SN65DSI84-Q1


    Initialization requires data lanes to be set to LP11 mode on startup and later switched to HS.
    Is this possible?


    The main question I am now left with, for the required configuration:

    What Command Mode Operation Channel and Virtual Channe    l do I need to use?


    Thanks again for your response, I hope you will be able to help us further.

  • 0 in reply to Student01HF

    Hi,

    Sending the framebuffer data from the GLCDC is transmission of images, i.e. video mode.

     

    Transition from LP to HS and back again is part of the MIPI specification.

     

    SN65DSI84 is not a Renesas part, sorry we cannot support this part.

    BR,

    NP_Renesas

  • 0 in reply to NP_Renesas

    Hello,

    Thanks for clarifying!

    I am not asking for specific support on the SN65DSI84...

    But I need to be able to switch my data lanes to LP11 mode for a short period and then be able to switch it back. I am having a lot of difficulty with the datasheet regarding this, could you perhaps explain how to do this and if perhaps any fo the builtin MIPI_DSI stack functions already do this?

    Currently I call the R_MIPI_DSI_Open() function to start the clock in HS mode, and later on call R_MIPI_DSI_Start() to start video mode, which I assumes sets the DSI data lanes in HS (video) mode.

    Is this correct?

    Kind regards

Reply
  • 0 in reply to NP_Renesas

    Hello,

    Thanks for clarifying!

    I am not asking for specific support on the SN65DSI84...

    But I need to be able to switch my data lanes to LP11 mode for a short period and then be able to switch it back. I am having a lot of difficulty with the datasheet regarding this, could you perhaps explain how to do this and if perhaps any fo the builtin MIPI_DSI stack functions already do this?

    Currently I call the R_MIPI_DSI_Open() function to start the clock in HS mode, and later on call R_MIPI_DSI_Start() to start video mode, which I assumes sets the DSI data lanes in HS (video) mode.

    Is this correct?

    Kind regards

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