RA0 SPI without interrupt

Hi DAV_94,

I think the official SAU_SPI sample project can fit your requirement, although it use the interrupt of SPI but in the interrupt it just read the status of SPI and not handling any data in IRQ.

ra-fsp-examples/example_projects/fpb_ra0e1/sau_spi/sau_spi_fpb_ra0e1_ep at v5.3.0.example.3 · renesas/ra-fsp-examples (github.com)

BR,

NP_Renesas

Ok thanks, which bit in which register can I check to verify that trasmission/reception has been completed?

You can check the TSF register:

And one more thing, sorry for my miss, the SAU_SPI cannot disable the interrupt because the transmit and reception is based on IRQ of SAU, so the most easy way to check if the data is transmitted is that when transmitting is done it will trigger an irq.

You can check the TSF register:

And one more thing, sorry for my miss, the SAU_SPI cannot disable the interrupt because the transmit and reception is based on IRQ of SAU, so the most easy way to check if the data is transmitted is that when transmitting is done it will trigger an irq.

So there is no other way to implement SPI without using interrupt and SAU:SPI Api? For the RA2 I was able to implement this

Yes, cause RA0 and RA2 are using different peripheral to implement SPI protocol, so on RA0 you have to enable the IRQ of SAU to implement the SPI function.

So there is no way to poll the SPI end-of-transimission neither start the SPI tx within a block that contains a __disable_irq( ); ?

Good morning, at the end we were able to implement the SPI WITHOUT  using interrupt. Here below a code example. Besides I noted that the code works if I the register R_SAU0 and not if I use g_spi0_ctrl.p_reg->SDR. After I gave a look at the code it seems that
p_reg is never initialized

_STATIC_INLINE_ uint16_t SPISendReceiveNOCallback( void )
{
  DisableInterrupt( );

  uint32_t spiTimeout   = UINT16_MAX;
  uint16_t receivedData = 0;

  /* Assert Slave select pin to start data transfer */
  CSAssert( );

  /* Write/Read data to/from ASIC */
  for ( uint8_t i = 0; i < SPI_NUM_BYTES; ++i )
  {
    /* Set the data and reset the timeout */
    spiTimeout                              = UINT16_MAX;
    R_SAU0->SDR[g_spi0_ctrl.p_cfg->channel] = spiTx[i];

    while ( R_SAU0->SSR_b[g_spi0_ctrl.p_cfg->channel].TSF != 0 )
    {
      --spiTimeout;
      if ( 0 == spiTimeout )
      {
        assert( false );
      }
    }

    /* Check for overflow error */
    uint16_t err_type = R_SAU0->SSR[g_spi0_ctrl.p_cfg->channel] & R_SAU0_SSR_OVF_Msk;
    if ( err_type != 0 )
    {
      R_SAU0->SIR[g_spi0_ctrl.p_cfg->channel] = err_type;
    }
    else
    {
      /* Read data */
      spiRx[i] = ( uint8_t )( R_SAU0->SDR[g_spi0_ctrl.p_cfg->channel] & UINT8_MAX );
    }
  }

  /* De-assert Slave select pin to stop data transfer */
  CSDeassert( );

  EnableInterrupt( );
  receivedData = ( uint16_t )( ( spiRx[0] << SHIFT_HIGH_BYTE ) | ( spiRx[1] ) );

  return receivedData;
}