ILGLERR (Illegal Command Error Flag) bit is set o the FSTATR2 (Flash Status Register 2 )during erase operation.

Team,

Controller: RA2L1
Product part number:  R7FA2L1AB2DFP

There were no error set on any of the register if I run my code via debugger. every thing was perfect if the code is run on debugger.
Code is running in this address: SRAM_1(RX) : ORIGIN = 0x20000000, LENGTH = 0x2000.

But the error will happen only if I upload this output file(.bin file) to the RAM and then if I perform flash erase using other software, then the above mentioned error is set( FSTATR2. EILGLERR bit).
Even though, I checked all the possibility for setting this error( FSTATR2. EILGLERR bit), but one of the conditions was not happened.

And all the registers related to the option setting memory were in default erased state (all are 0xFF)

First I performed write then I performed chip erase via debugger which is succeeded without any error, then I tried to perform the same using other flash programmer using that generated output file(.BIN file).
After debugging I got to know that the error was set immediately after setting the command, till there everything was OK, I have given the code below.

Please help me to figure out the issue.

Thank you in advance for the explanation to my question

Comments:
Mode Code flash Data flash
----------------------------------------------
Mode 1 : Read Mode Read Mode
Mode 2 : Program/Erase Mode Read Mode
Mode 3 : Read Mode Program/Erase Mode
********************************************************************************/
int ModeChange(BYTE mode)
{
int i,t;

switch(mode)
{
case 1: // Read mode
/* Make Data flash in read mode
Set DFLCTL.DFLEN bit
*/
regwrite8(DFLCTL, (regread8(DFLCTL) & ~(DFLEN_MASK) | DFLEN_MASK));

if(regread8(DFLCTL) != DFLEN_MASK)
return 1; // Failed to make transition to read mode

/* Make the code flash in read mode */
regwrite8(FPR, 0xA5);
regwrite8(FPMCR, (regread8(FPMCR) & ~(CODE_DATA_FLASH_PE_MASK) | 0x08));
regwrite8(FPMCR, 0xF7);
regwrite8(FPMCR, (regread8(FPMCR) & ~(CODE_DATA_FLASH_PE_MASK) | 0x08));

/* Wait for tMS(2us) */
for(t=0;t<0x100;t++);

if(regread8(FPMCR) != 0x08)
return 2; // Failed to make Code flash in read mode

/* Write AA00h to FENTRYR register */
regwrite16(FENTRYR, 0xAA00);

/* FENTRYR = 0x0000? */
i = 0;
while(1)
{
if(regread16(FENTRYR) == 0x0000) break;
if(i > TIMEOUTTIME) return 3; // Failed to make the transition to Code flash read mode/timeout
i++;
}
break;

case 2: // Code flash P/E mode
/* Write 0xAA01 to FENTRYR register */
regwrite16(FENTRYR, 0xAA01);

if(regread16(FENTRYR) != 0x01)
return 4; // Failed to make transition to code flash P/E mode

/* Write 02h to FPMCR register */
regwrite8(FPR, 0xA5);
regwrite8(FPMCR, regread8(FPMCR) & ~(CODE_DATA_FLASH_PE_MASK) | 0x02);
regwrite8(FPMCR, 0xFD);
regwrite8(FPMCR, regread8(FPMCR) & ~(CODE_DATA_FLASH_PE_MASK) | 0x02);

/* Wait for tDIS(2us) */
for(t=0;t<0x100;t++);

if(regread8(FPMCR) != 0x02)
return 5; // Failed to switch the mode to code flash P/E

/* Protection Unlock Status Register
When the FPMCR register is not accessed as described in the procedure to unlock protection,
data is not written to the register and this flag is set to 1.
*/
if(regread8(FPSR) == 0x01)
return 6; // Procedure to unlock protection for FPMCR is failed
break;

case 3: // Data flash P/E mode
/* Write 0xAA80 to FENTRYR register */
regwrite16(FENTRYR, 0xAA80);

if(regread16(FENTRYR) != 0x80)
return 7; // Failed to make transition to data flash P/E mode

/* Wait for tDSTOP */
for(t=0;t<0x100;t++);

/* Data P/E mode */
regwrite8(FPR, 0xA5);
regwrite8(FPMCR, (regread8(FPMCR) & ~(CODE_DATA_FLASH_PE_MASK) | 0x10));
regwrite8(FPMCR, 0xEF);
regwrite8(FPMCR, (regread8(FPMCR) & ~(CODE_DATA_FLASH_PE_MASK) | 0x10));

/* Wait for tDIS(2us) */
for(t=0;t<0x100;t++);

/* Protection Unlock Status Register
When the FPMCR register is not accessed as described in the procedure to unlock protection,
data is not written to the register and this flag is set to 1.
*/
if(regread8(FPSR) == 0x01)
return 8; // Procedure to unlock protection for FPMCR is failed
break;

default: break;
}

return 0;
}

int FlashErase(void)
{
int ret = 0, t;

if(ModeChange(2)){
ret = 1;
goto error;
}

#if defined (CLOCK_24MHZ)
/* Set frequency in FISR.PCKA bit
The hardware sequencer for the flash programming executes the commands according to the PCKA[5:0] bits. For this reason,
it is necessary to set the PCKA[5:0] bits according to Flash-IF clock (ICLK) before execution of the programming
and not during the programming.
*/
/* A wrong frequency setting may cause the flash macro to be damaged
Please confirm before change
*/
regwrite8(FISR, (regread8(FISR) & ~(PCKA_MASK)) | PCKA_24MHz);

#elif defined (CLOCK_2MHZ) // 2 MHz clock
/* Set freqency in FISR.PCKA bit */
regwrite8(FISR, (regread8(FISR) & ~(PCKA_MASK)) | PCKA_2MHz);
#else // CLOCK 8MHZ
/* Set freqency in FISR.PCKA bit */
regwrite8(FISR, (regread8(FISR) & ~(PCKA_MASK)) | PCKA_8MHz);
#endif

/* Set start and end address of the target chip area */
regwrite16(FSARH, ((WORD)(PE_StartAddress >> 16) & 0xFFFF));
regwrite16(FSARL, ((WORD)(PE_StartAddress) & 0xFFFF));
regwrite16(FEARH, ((WORD)((PE_StartAddress + FlashMemorySize - 1) >> 16) & 0xFFFF));
regwrite16(FEARL, (WORD)(PE_StartAddress + FlashMemorySize - 1) & 0xFFFF);

/* Write (86h: for chip erase) to FCR register
Set the Software Command Setting bit(CMD[3:0]) to chip erase and
start processing by setting OPSTbit(Processing Start bit)
*/
regwrite8(FCR, FLASH_CHIP_ERASE);

if(regread8(FCR) != FLASH_CHIP_ERASE){
ret = 6;
goto error;
}

/* FSTATR1.FRDY bit = 1? */
if(Wait_FRDY(1)){
ret = 2;
goto error;
}

/* Write 00h to FCR register */
regwrite8(FCR, 0x06);
regwrite8(FCR, 0x00);

/* FSTATR1.FRDY bit = 0? */
if(Wait_FRDY(0)){
ret = 3;
goto error;
}

/* (FSTATR2.ILGLERR bit = 0?) and (FSTATR2.ERERR bit = 0?) */
if(regread16(FSTATR2) & 0x11){
ret = 4;
goto error;
}

error:
/* Change the flash mode to ReadMode */
if(ModeChange(1))
ret = 5;

return ret;
}