Open drain pin configuration for GPIO P22/P23 Rx130 part number R5F51306B

We are using RX130 controller part number R5F51306B for one of our projects. We have developed our customized development board in which there is no external circuit connected to controller pins.

So, any external devices/interface such as EEPROM, RTC etc., that are going to be connected to controller; those are having their own small PCBs and circuits on them, and we then connect their input/output directly controller pins.

 I am facing an issue with open drain configuration for couple of IOs as listed below –

Our understanding of Open Drain –

  1. Unless external pull up is connected to these pins pin shall not be driven high

 Is this understanding, correct?

 Issue I am facing –

 Even though I have not connected any external pull-up to above pins I see pin can be toggled between HIGH and LOW.

Still issue persists!!

Also, I see ODR0 register have correct configuration (B6 & B4 bit in ODR0 must be set to 1 for open drain as per datasheet).

Still open drain configuration functionality is not as expected.

  • Hello Satish

    Thank you for reaching out the Renesas Engineering Community! You are correct; P22 and P23 are both open drain GPIOs of RX130. Can you also elaborate your issue more? How did you set your pins? Are they INPUT or OUTPUT? How is your PDR registers configured?

    Open-Drain Circuit Explanation:

    An open-drain circuit is a type of output circuit that can only actively pull the output low (connect it to ground), but it cannot actively drive the output high (connect it to the supply voltage). When the output is in its inactive state, it effectively disconnects from both the ground and supply voltage, leaving it in a high-impedance state. To achieve this behavior, open-drain circuits typically use a transistor (usually a MOSFET) that connects the output pin to ground when turned on.

    Here's how it works:

    • Pull Low (Active State): The open-drain output actively connects to ground (logic 0) when the transistor is turned on. This is achieved by applying a logic low signal to the control terminal of the transistor.

    • High-Impedance (Inactive State): In the inactive state, the transistor is turned off, disconnecting the output pin from both the ground and supply voltage. In this state, the pin effectively becomes an input, allowing external pull-up resistors to pull it to a logic high level (Vcc).

    I hope this helps!


    If this response, or one provided by another user, answers your question, please verify the answer. Thank you!
    Renesas Engineering Community Moderators

  • Hello Jef,

    Thank you for your prompt response!!

    Actually, I tried attaching screenshots of configuration of smart configurator, but it failed. It looks like pin was getting toggled because we were using logic analyzer to capture trace. The logic analyzer has its internal pull-up register because of which pin was getting toggled.

    When pin was connected to oscilloscope pin behavior is as expected. Kieran Slorach from Renesas asked us to use scope instead of analyzer which pointed out that issue is not in pin configuration but in analyzer.

    Best Regards,


  • Hi Satish.

    Thanks for sharing this here. I'm sure it will be insightful for the community. If your problem is solved, can we consider this thread closed? Let us know.


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