custom G2UL Board - Uboot logs not coming

Hi Renesas Team,

We have designed our custom board based on RZG2UL CPU and we are not getting u-boot logs.

We have used G2UL Type 1 (Part Number: R9A07G043U15GBG) as a CPU, Micron 2GB DDR4 (Part Number : MT40A1G16KD-062E IT:E) and Renesas Dialogue Quad SPI Flash (Part Number : AT25SF321B)

We have not swapped DDR4 pins between SOC and DDR and connected them one to one only. We refereed  "https://renesas.info/wiki/RZ-G/RZ-G2_BSP_Porting_FlashWriter".  We did Code changes and added support of our QSPI Flash Device ID.

We updated "RZG2L_G2UL_Five_A3UL_DDR_config_generation_tool_v3.0.1.xlsm" file and generated  param_mc_C-011_D4-01-1.c and param_swizzle_T3bcud2.c  based on conditions ,connections and topology as per our custom design. After doing this we have build flash writer and getting Flash_Writer_SCIF_RZG2UL_SMARC_DDR4_1GB_1PCS.mot which I have flashed through SCIF download mode.

After doing this I have run  DDRCK command it shows as pass so it seems that DDR is working ok.

>DDRCK
=== DDR R/W CHECK ====
Check:0x00_41000000 ... Pass!
>

Issue 1 : SCIF Boot

--------------------------------

Then after I have followed below steps to write boot loader files into QSPI flash as per r01us0556ej0102-rz-g(Board_StartUp_Guide_smarcEVK).pdf (attached here)r01us0556ej0102-rz-g(Board_StartUp_Guide_smarcEVK) (1).pdf

Below are logs of minicom.

Welcome to minicom 2.7.1

OPTIONS: I18n
Compiled on Aug 13 2017, 15:25:34.
Port /dev/ttyUSB0, 17:10:04

Press CTRL-A Z for help on special keys

SCIF Download mode
(C) Renesas Electronics Corp.
-- Load Program to System RAM ---------------
please send !

Flash writer for RZ/G2 Series V1.06 Aug.10,2022
Product Code : RZ/G2UL Type1
>XLS2
command not found
>XLS2
===== Qspi writing of RZ/G2 Board Command =============
Load Program to Spiflash
Writes to any of SPI address.
Dialog : 00008701
AT25SF321B
Program Top Address & Qspi Save Address
===== Please Input Program Top Address ============
Please Input : H'11E00

===== Please Input Qspi Save Address ===
Please Input : H'00000
Work RAM(H'50000000-H'53FFFFFF) Clear....
please send ! ('.' & CR stop load)
SPI Data Clear(H'FF) Check :H'00000000-0000FFFF Erasing..Erase Completed
SAVE SPI-FLASH.......
======= Qspi Save Information =================
SpiFlashMemory Stat Address : H'00000000
SpiFlashMemory End Address : H'0000C990
===========================================================

>XLS2
===== Qspi writing of RZ/G2 Board Command =============
Load Program to Spiflash
Writes to any of SPI address.
Dialog : 00008701
AT25SF321B
Program Top Address & Qspi Save Address
===== Please Input Program Top Address ============
Please Input : H'00000

===== Please Input Qspi Save Address ===
Please Input : H'1D200
Work RAM(H'50000000-H'53FFFFFF) Clear....
please send ! ('.' & CR stop load)
SPI Data Clear(H'FF) Check :H'00010000-000CFFFF Erasing.............Erase Completed
SAVE SPI-FLASH.......
======= Qspi Save Information =================
SpiFlashMemory Stat Address : H'0001D200
SpiFlashMemory End Address : H'000CA00F
===========================================================

>

Address which we are used is suggested in Renesas EVK document. Can you please check above used address is correct for our renesas QSPI Flash (AT25SF321B) ?

We used bl2_bp-smarc-rzg2ul.srec and fip-smarc-rzg2ul.srec files as per mentioned in SCIF testing but after doing above all steps and setting QSPI boot mode,  we are still not able to get u-boot logs.

We only got below messages:

NOTICE: BL2: v2.6(release):7e8696ff4-dirty
NOTICE: BL2: Built : 12:56:41, Dec 26 2022

Can you please suggest us how to resolve above issue?

SD Boot mode:

---------------------

We have connected SD Card on SD0 interface of soc.

We used "https://renesas.info/wiki/RZ-G/RZ-G2L_SMARC#SD_card_boot " reference and followed all steps for SD Boot.

Can you guide us how to save DDR4 pin mapping configuration permanently when we are using SD Boot?  new configurations of DDR4 applies in SCIF mode only but as soon we power off and re power on changing boot mode to SD Boot mode We are not able to see U-boot.

In SD Card boot also, We are getting same below log as QSPI boot.

NOTICE: BL2: v2.6(release):7e8696ff4-dirty
NOTICE: BL2: Built : 12:56:41, Dec 26 2022

Can you please suggest how to complete SD Boot along with DDR4 pin mapping,  uboot and kernel?

Thanks,

Maulik

Top Replies

  • Address which we are used is suggested in Renesas EVK document. Can you please check above used address is correct for our renesas QSPI Flash (AT25SF321B) ?

    Address is the same for all SPI Flash devices.

    We only got below messages:

    NOTICE: BL2: v2.6(release):7e8696ff4-dirty
    NOTICE: BL2: Built : 12:56:41, Dec 26 2022

    Can you please suggest us how to resolve above issue?

    It is probably DDR inti. Make sure you copy the DDR init files that worked with flash writer to Trusted Firmware-ARM

    https://renesas.info/wiki/RZ-G/RZ-G2_BSP_Porting_ATF#/G2L,_/V2L

    If you really cannot figure it out, you can try using JTAG. https://renesas.info/wiki/RZ-G/RZG_debug

    Can you guide us how to save DDR4 pin mapping configuration permanently when we are using SD Boot?  new configurations of DDR4 applies in SCIF mode only but as soon we power off and re power on changing boot mode to SD Boot mode We are not able to see U-boot.

    That is you issue. You need to put the DDR settings in both Flash writer code and Trusted Firmware-ARM code. If DDR is working in Flash writer, then copy the files to TF-A.

    Can you please suggest how to complete SD Boot along with DDR4 pin mapping,  uboot and kernel?

    Pin mapping for DDR is handled in TF-A code. So, you don't have to care about DDR pin mapping in u-boot and kernel.

  • Hi Chris,

    Thank you for quick update. I refereed "https://renesas.info/wiki/RZ-G/RZ-G2_BSP_Porting_ATF#/G2L,_/V2L" and found that smarc-G2UL board is not supported in Trusted Firmware-ARM github code. Later I visited "">renesas.info/.../RZ-G2L_SMARC link and I found that smarc-G2Ul board is supported in their code version of Trusted Firmware code.

    Now, I copied DDR init files in Trusted Firmware-ARM code with log level 40 and  built the TFA code. After building I performed below steps:

    sudo dd if=bootparams-smarc-rzg2ul.bin of=/dev/sdd seek=1 count=1
    sudo dd if=bl2-smarc-rzg2ul.bin of=/dev/sdd seek=8
    sudo dd if=fip-smarc-rzg2ul.bin of=/dev/sdd seek=128
    sudo dd if=u-boot.bin of=/dev/sdd seek=1532
    sync

    Here below is the output after I set SD card boot option selected and power on the board:

    bootlogs_rzg2ul.txt
    NOTICE: BL2: v2.6(release):7e8696ff4-dirty
    NOTICE: BL2: Built : 11:08:57, Mar 24 2023
    INFO: BL2: Doing platform setup
    INFO: Configuring TrustZone Controller
    INFO: Total 1 regions set.
    INFO: Configuring TrustZone Controller
    INFO: Total 1 regions set.
    INFO: BL2: setup DDR (Rev. 2.09)
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 99
    INFO: BL2: window_0 = 27, window_1 = 29, window_diff = 2
    INFO: BL2: CURRENT BEST VREF PHY side :99
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 99
    INFO: BL2: window_0 = 28, window_1 = 28, window_diff = 0
    INFO: BL2: CURRENT BEST VREF PHY side :99
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 98
    INFO: BL2: window_0 = 27, window_1 = 30, window_diff = 3
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 98
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 97
    INFO: BL2: window_0 = 26, window_1 = 30, window_diff = 4
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 97
    INFO: BL2: window_0 = 26, window_1 = 30, window_diff = 4
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 96
    INFO: BL2: window_0 = 25, window_1 = 30, window_diff = 5
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 96
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 95
    INFO: BL2: window_0 = 25, window_1 = 31, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 95
    INFO: BL2: window_0 = 26, window_1 = 30, window_diff = 4
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 94
    INFO: BL2: window_0 = 25, window_1 = 31, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 94
    INFO: BL2: window_0 = 24, window_1 = 31, window_diff = 7
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 93
    INFO: BL2: window_0 = 25, window_1 = 32, window_diff = 7
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 93
    INFO: BL2: window_0 = 25, window_1 = 31, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 92
    INFO: BL2: window_0 = 25, window_1 = 32, window_diff = 7
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 92
    INFO: BL2: window_0 = 25, window_1 = 31, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 91
    INFO: BL2: window_0 = 23, window_1 = 32, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 91
    INFO: BL2: window_0 = 24, window_1 = 32, window_diff = 8
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 90
    INFO: BL2: window_0 = 23, window_1 = 32, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 90
    INFO: BL2: window_0 = 24, window_1 = 32, window_diff = 8
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 89
    INFO: BL2: window_0 = 23, window_1 = 33, window_diff = 10
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 89
    INFO: BL2: window_0 = 24, window_1 = 32, window_diff = 8
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 88
    INFO: BL2: window_0 = 22, window_1 = 33, window_diff = 11
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 88
    INFO: BL2: window_0 = 24, window_1 = 33, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 87
    INFO: BL2: window_0 = 22, window_1 = 33, window_diff = 11
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 87
    INFO: BL2: window_0 = 23, window_1 = 32, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 86
    INFO: BL2: window_0 = 22, window_1 = 35, window_diff = 13
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 86
    INFO: BL2: window_0 = 22, window_1 = 34, window_diff = 12
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 85
    INFO: BL2: window_0 = 22, window_1 = 34, window_diff = 12
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 85
    INFO: BL2: window_0 = 22, window_1 = 34, window_diff = 12
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 84
    INFO: BL2: window_0 = 20, window_1 = 35, window_diff = 15
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 84
    INFO: BL2: window_0 = 21, window_1 = 34, window_diff = 13
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 83
    INFO: BL2: window_0 = 21, window_1 = 35, window_diff = 14
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 83
    INFO: BL2: window_0 = 21, window_1 = 35, window_diff = 14
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 82
    INFO: BL2: window_0 = 21, window_1 = 35, window_diff = 14
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 82
    INFO: BL2: window_0 = 21, window_1 = 36, window_diff = 15
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 100
    INFO: BL2: window_0 = 27, window_1 = 29, window_diff = 2
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 100
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 101
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: CURRENT BEST VREF PHY side :101
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 101
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 102
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 102
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 103
    INFO: BL2: window_0 = 28, window_1 = 28, window_diff = 0
    INFO: BL2: CURRENT BEST VREF PHY side :103
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 103
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 104
    INFO: BL2: window_0 = 28, window_1 = 28, window_diff = 0
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 104
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 105
    INFO: BL2: window_0 = 29, window_1 = 28, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 105
    INFO: BL2: window_0 = 29, window_1 = 27, window_diff = 2
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 106
    INFO: BL2: window_0 = 29, window_1 = 28, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 106
    INFO: BL2: window_0 = 29, window_1 = 27, window_diff = 2
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 107
    INFO: BL2: window_0 = 29, window_1 = 28, window_diff = 1
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 107
    INFO: BL2: window_0 = 29, window_1 = 26, window_diff = 3
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 108
    INFO: BL2: window_0 = 29, window_1 = 26, window_diff = 3
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 108
    INFO: BL2: window_0 = 29, window_1 = 25, window_diff = 4
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 109
    INFO: BL2: window_0 = 29, window_1 = 26, window_diff = 3
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 109
    INFO: BL2: window_0 = 30, window_1 = 25, window_diff = 5
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 110
    INFO: BL2: window_0 = 31, window_1 = 26, window_diff = 5
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 110
    INFO: BL2: window_0 = 31, window_1 = 25, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 111
    INFO: BL2: window_0 = 31, window_1 = 26, window_diff = 5
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 111
    INFO: BL2: window_0 = 30, window_1 = 25, window_diff = 5
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 112
    INFO: BL2: window_0 = 31, window_1 = 26, window_diff = 5
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 112
    INFO: BL2: window_0 = 31, window_1 = 24, window_diff = 7
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 113
    INFO: BL2: window_0 = 31, window_1 = 25, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 113
    INFO: BL2: window_0 = 32, window_1 = 24, window_diff = 8
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 114
    INFO: BL2: window_0 = 31, window_1 = 24, window_diff = 7
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 114
    INFO: BL2: window_0 = 32, window_1 = 23, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 115
    INFO: BL2: window_0 = 31, window_1 = 25, window_diff = 6
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 115
    INFO: BL2: window_0 = 32, window_1 = 23, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 0, current_vref = 116
    INFO: BL2: window_0 = 33, window_1 = 24, window_diff = 9
    INFO: BL2: PHY side VREF training passed on lane 1, current_vref = 116
    INFO: BL2: window_0 = 33, window_1 = 23, window_diff = 10
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 38
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: CURRENT BEST VREF DRAM side :38
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 38
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: CURRENT BEST VREF DRAM side :38
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 37
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: CURRENT BEST VREF DRAM side :37
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 37
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: CURRENT BEST VREF DRAM side :37
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 36
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 36
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: CURRENT BEST VREF DRAM side :36
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 35
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 35
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 34
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 34
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 33
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 33
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 32
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 32
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 31
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 31
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 30
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 30
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 29
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 29
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 28
    INFO: BL2: window_0 = 24, window_1 = 30, window_diff = 6
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 28
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 27
    INFO: BL2: window_0 = 25, window_1 = 30, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 27
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 26
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 26
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 25
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 25
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 24
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 24
    INFO: BL2: window_0 = 25, window_1 = 29, window_diff = 4
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 23
    INFO: BL2: window_0 = 24, window_1 = 30, window_diff = 6
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 23
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 22
    INFO: BL2: window_0 = 24, window_1 = 30, window_diff = 6
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 22
    INFO: BL2: window_0 = 24, window_1 = 29, window_diff = 5
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 39
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 39
    INFO: BL2: window_0 = 26, window_1 = 29, window_diff = 3
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 40
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 40
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 41
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: CURRENT BEST VREF DRAM side :41
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 41
    INFO: BL2: window_0 = 27, window_1 = 29, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 42
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 42
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 43
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 43
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 44
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 44
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 45
    INFO: BL2: window_0 = 27, window_1 = 28, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 45
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: CURRENT BEST VREF DRAM side :45
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 46
    INFO: BL2: window_0 = 26, window_1 = 28, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 46
    INFO: BL2: window_0 = 26, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 47
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: CURRENT BEST VREF DRAM side :47
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 47
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 48
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 48
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 49
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 49
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 50
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 50
    INFO: BL2: window_0 = 27, window_1 = 27, window_diff = 0
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 51
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 51
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 52
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 52
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 53
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 53
    INFO: BL2: window_0 = 29, window_1 = 27, window_diff = 2
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 54
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: VREF training passed during VrefDQ training DRAM side, current_vref = 54
    INFO: BL2: window_0 = 28, window_1 = 27, window_diff = 1
    INFO: BL2: Loading image id 3
    NOTICE: BL2: SD boot from partition 0
    NOTICE: BL2: Load dst=0x1f6a0 src=(p:0)0x10000(128) len=0x10(1)
    NOTICE: BL2: SD boot from partition 0
    NOTICE: BL2: Load dst=0x1f820 src=(p:0)0x10010(128) len=0x28(1)
    INFO: Loading image id=3 at address 0x44000000
    NOTICE: BL2: SD boot from partition 0
    NOTICE: BL2: Load dst=0x44000000 src=(p:0)0x10090(128) len=0x6069(49)
    INFO: Image id=3 loaded: 0x44000000 - 0x44006069
    INFO: BL2: Loading image id 5
    NOTICE: BL2: SD boot from partition 0
    NOTICE: BL2: Load dst=0x1f6a0 src=(p:0)0x10000(128) len=0x10(1)
    NOTICE: BL2: SD boot from partition 0
    NOTICE: BL2: Load dst=0x1f820 src=(p:0)0x10010(128) len=0x28(1)
    NOTICE: BL2: Load dst=0x1f820 src=(p:0)0x10038(128) len=0x28(1)
    INFO: Loading image id=5 at address 0x50000000
    NOTICE: BL2: SD boot from partition 0
    NOTICE: BL2: Load dst=0x50000000 src=(p:0)0x16100(176) len=0xa6d08(1336)
    INFO: Image id=5 loaded: 0x50000000 - 0x500a6d08
    NOTICE: BL2: Booting BL31
    INFO: Entry point address = 0x44000000
    INFO: SPSR = 0x3cd
    NOTICE: BL31: v2.6(release):7e8696ff4-dirty
    NOTICE: BL31: Built : 11:08:57, Mar 24 2023
    INFO: Configuring TrustZone Controller
    INFO: Total 1 regions set.
    INFO: Configuring TrustZone Controller
    INFO: Total 1 regions set.
    INFO: GICv3 without legacy support detected.
    INFO: ARM GICv3 driver initialized in EL3
    INFO: Maximum SPI INTID supported: 511
    INFO: BL31: Initializing runtime services
    INFO: BL31: Preparing for EL3 exit to normal world
    INFO: Entry point address = 0x50000000
    INFO: SPSR = 0x3c5
    
    
    U-Boot 2021.10-g83b2ea37f4-dirty (Mar 24 2023 - 11:08:34 +0530)
    
    CPU: Renesas Electronics K rev 16.15
    Model: smarc-rzg2ul
    DRAM: 896 MiB
    ### ERROR ### Please RESET the board ###
    


    U-Boot 2021.10-g83b2ea37f4-dirty (Mar 24 2023 - 11:08:34 +0530)

    CPU: Renesas Electronics K rev 16.15
    Model: smarc-rzg2ul
    DRAM: 896 MiB
    ### ERROR ### Please RESET the board ###

    Can you please suggest what other changes are required to boot completely in u-boot mode?

    Thanks,

    Maulik Manvar

  • DDR seems to be configured correctly, even though in u-boot only half  of what you have installed is reported.

    Most likely you are stuck in the board_init function of rzg2ul-dev.c (board/renesas/rzg2ul-dev folder), I would have a look there.

  • Hi MicBis,

    Thank you so much to pointing out the root cause. Now I can access u-boot. As of now I am facing one issue related SD Card voltage.

    Kernel get stuck at below part:

    [ 2.144621] renesas_sdhi_internal_dmac 11c10000.mmc: mmc1 base at 0x0000000011c10000, max clock rate 100 MHz
    [ 2.161615] Waiting for root device /dev/mmcblk0p2...
    [ 2.240451] mmc1: new HS200 MMC card at address 0001
    [ 2.246112] mmcblk1: mmc1:0001 TB2916 14.6 GiB
    [ 2.251087] mmcblk1boot0: mmc1:0001 TB2916 partition 1 4.00 MiB
    [ 2.257169] mmcblk1boot1: mmc1:0001 TB2916 partition 2 4.00 MiB
    [ 2.263337] mmcblk1rpmb: mmc1:0001 TB2916 partition 3 4.00 MiB, chardev (242:0)

    It seems that during kernel sdhi interface needs 1.8V and we are getting 3.3V. Can you please help to setup pmic output to 1.8V from 3.3V in kernel device tree? Please see below diagram for providing supply to sdhi in our design.

    I2C address of pmic is 0x30 and we do not have used any gpio for pmic to change voltage states.

    Can you guide us what can be the issue ?

    Thanks,

    Maulik Manvar

  • In your device tree, just add this to your sdhi node:

        no-1-8-v; 

    Then it will keep your card at 3.3 volts.

    As for help with the PMIC, no one on this forum will know about PMIC settings. You will have to contract a Renesas FAE for that.

    Chris

  • I think that you can try to replace the regulator-gpio and use this:

    https://www.kernel.org/doc/Documentation/devicetree/bindings/mfd/rn5t618.txt

    github.com/.../rn5t618-regulator.c

    That looks similar to what you are using, it's not a Renesas PMIC.

  • Hi Team,

    I have resolved 3.3V to 1.8V switching issue. Now I am getting 1.8V at required sdhi interface but still my kernel log is stopped after below message. 

    [ 2.137219] Waiting for root device /dev/mmcblk0p2...

    I have checked bootargs and bootcmd variables and sd card is accessible during uboot part.

    bootargs=rw rootwait earlycon root=/dev/mmcblk0p2
    bootcmd=mmc dev 0;fatload mmc 0:1 0x48080000 Image-smarc-rzg2ul.bin;fatload mmc 0:1 0x48000000 Image-r9a07g043u11-smarc.dtb; booti 0x48080000 - 0x48000000

    => ls mmc 0:1
    17488384 Image-smarc-rzg2ul.bin
    30094 Image-r9a07g043u11-smarc.dtb

    2 file(s), 0 dir(s)

    It seems like my sd card is not detecting after kernel initialisation. 

    We have connected SD card CD pin with io expander and it is written under i2c2 node. 

    We are using DAT0 to DAT3 with SD Card and we have mounted pull up on these signals while on DAT4 to DAT7 we have kept provision only of pull up and kept as DNI.

    Here below are my device tree changes for sd card. Can you please suggest what changes are missing here to resolve kernel booting issue ?

    sdcard_devicetreechanges.txt
    &sdhi0 {
    	pinctrl-0 = <&sdhi0_pins>;
    	pinctrl-1 = <&sdhi0_pins_uhs>;
    	pinctrl-names = "default", "state_uhs";
    
    	vmmc-supply = <&vdd_sd0>;
    	vqmmc-supply = <&vccq_sdhi0>;
    	bus-width = <4>;
    	status = "okay";
    	disable-wp;
    };
    
    
    vdd_sd0: regulator-1 {
    	compatible = "regulator-fixed";
    	regulator-name = "vdd_sd0";
    	regulator-min-microvolt = <1000000>;
    	regulator-max-microvolt = <1800000>;
    	regulator-boot-on;
    	vin-supply = <&reg_1p8v>;
    };
    
    vccq_sdhi0: regulator-vccq-sdhi0 {
    	compatible = "regulator-gpio";
    	regulator-name = "SDHI0 VccQ";
    	regulator-min-microvolt = <1800000>;
    	regulator-max-microvolt = <3300000>;
    	gpios = <&exp1 11 GPIO_ACTIVE_LOW>;
    	gpios-states = <1>;
    	states = <3300000 1
    	1800000 0>;
    };
    
    
    
    //IO Expander
    exp1: gpio@23 {
                    compatible = "ti,tca6424";
                    reg = <0x23>;
                    gpio-controller;
                    #gpio-cells = <2>;
    
                    interrupt-parent = <&pinctrl>;
                    interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
                    interrupt-controller;
                    #interrupt-cells = <2>;
    
                    /*pinctrl-names = "default";
                    pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;*/
    };
    
    

    Thanks,

    Maulik Manvar

  • Full log? 

    Is the card detected?

  • Hi MicBis and Chris,

    Thank you for providing support on this issue. Issue is resolved now and now able to log into root. I just needed to configure sd card vmmc-supply with regulator-fixed 3.3V and needed to update vqmmc-supply as regulator-gpio by providing 

    gpios-states = <0>;
    states = <3300000 1
    1800000 0>;

    Thanks,

    Maulik Manvar