EKRA4M2 Clock Control with CGC Module

Hello,

I want to configure clock settings in a function using function parameter frequency.

When I try to find division ratio for PCLKD module by calculating, then I assign it to the pclkd_div structure member.

My desired pclkd_div value is 4, I saw it CGC_SYS_CLOCK_DIV_16 on debug screen.

However, when I observe it in debug screen, it doesn't seem having the right calculated value. 

My Codes are below:

cgc_divider_cfg_t clkDiv;
cgc_clock_t cgcClock;
fsp_err_t err;
uint32_t frequency = 50000000;
uint32_t pclkd_value = 0;

/* Clock configuration structure */
cgc_clocks_cfg_t clocks_cfg = {0};

/* Open the CGC module */
err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
assert(FSP_SUCCESS == err);

/* Set the system clock to PLL and configure PLL */
clocks_cfg.system_clock = CGC_CLOCK_PLL;
clocks_cfg.pll_state = CGC_CLOCK_CHANGE_NONE;
clocks_cfg.pll_cfg.source_clock = CGC_CLOCK_MAIN_OSC;
clocks_cfg.pll_cfg.multiplier = 25; // PLL multiplier (8 MHz * 25 = 200 MHz)
clocks_cfg.pll_cfg.divider = 3; // PLL output divider (200 MHz / 2 = 100 MHz)

R_CGC_SystemClockGet(&g_cgc0_ctrl, &cgcClock, &clkDiv);

/* Set the divisors for peripheral clocks */
clocks_cfg.divider_cfg.sckdivcr_b.iclk_div = clkDiv.sckdivcr_b.iclk_div; 
clocks_cfg.divider_cfg.sckdivcr_b.pclka_div = clkDiv.sckdivcr_b.pclka_div; 
clocks_cfg.divider_cfg.sckdivcr_b.pclkb_div = clkDiv.sckdivcr_b.pclkb_div; 
clocks_cfg.divider_cfg.sckdivcr_b.pclkc_div = clkDiv.sckdivcr_b.pclkc_div; 
pclkd_value = ((24000000 * clocks_cfg.pll_cfg.multiplier) / clocks_cfg.pll_cfg.divider) / (frequency);
clocks_cfg.divider_cfg.sckdivcr_b.pclkd_div = pclkd_value;
clocks_cfg.divider_cfg.sckdivcr_b.bclk_div = clkDiv.sckdivcr_b.bclk_div; 
clocks_cfg.divider_cfg.sckdivcr_b.fclk_div = clkDiv.sckdivcr_b.fclk_div; 

/* */
clocks_cfg.mainosc_state = CGC_CLOCK_CHANGE_NONE;
clocks_cfg.hoco_state = CGC_CLOCK_CHANGE_NONE;
clocks_cfg.moco_state = CGC_CLOCK_CHANGE_NONE;
clocks_cfg.loco_state = CGC_CLOCK_CHANGE_NONE;
clocks_cfg.pll_state = CGC_CLOCK_CHANGE_NONE;

/* Apply the clock configuration */
err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &clocks_cfg);
assert(FSP_SUCCESS == err);

/*Starts GPT*/
R_GPT_Open(pGpt, &gptCfgPWM);
R_GPT_Start(pGpt);