In the custom board while checking the ethernet pin we are facing the error with the ethernet all the pin of the EVK and our custom boards are same the only difference between the those two boards where the reset pin the EVK has the reset pin as 706 and our board has 404. i am trying the ethernet_ek_ra8m1 sample code it shows the network is down even after i connect the the ethernet which is working fine with the EVK,can you tell me how to configure the RESET pin in the sample code or why i am facing this issue
Hii mukesh The issue is likely due to the difference in the Ethernet PHY reset pin between the EVK and your custom board. Since EVK uses P706, but your custom board uses P404, you need to modify the pin configuration in your application. Have you did it ? also i suggest you to check the behavior of reset pin using logic analyzer.Kind Regards,
P706
P404
GN_Renesas
Hii mukesh
I need one more clarification regarding the schematic in the clock circuit—is the 10k component a resistor or a ferrite bead?
Regards,
That is the resistor,The problem is not solved yet
I just want to know have you followed the ethernet design guide by renesas ?RA Ethernet Design and Custom PHY Setup using FSPPlease check out this and let me know if the issue solves. and can you mention the part number of clock ic you are using ?
Kind Regards,
This is the pin configuration we are using in the custom board. while uploading the code with the EVK board both the leds are turing on when the ethernet cable is connected but in the custom board the yellow LEDs are high even before the ethernet cable is connected. I am using the sample Ethernet code for the testing does i need to modify anything in the code for the custom board both the reset pin of the EVK and the Custom board are same the remaining are as in the above picture.Can you guide me to solve this issue
Try connecting the SWD clock pin to the MD pin. Many customers have encountered this issue before. The problem arises when trying to access Ethernet, as some registers are located in the TrustZone section of the MCU. To access TrustZone via SWD on the customer's board, the MD pin and SWD clock pin should be shorted. Please give this a try and let me know if it resolves the issue.
No Sir, It doesn't solve m problem even now I am still facing the same error
Hello mukesh
We are looking into your issue Could you please let us know if the custom board has serial programing interface connection require for TrustZone, DLM state change and IDAU boundaries configuration used by Ethernet and EDMAC peripherals? for further problem investigations.
Yes we have SWD interface Jtag pins. We are using aws http example code of fsb itself code converted for our custom board pins and we didnt make any other changes. Pls guide how to get DLM & IDAU boudaries how do we configure. our ethernet pins are mixed config as attached circuit and config, Do you think this can cause the issue but no warning in e2studio
Hii mukesh Jeyakumar
Please check below feedback and let us know if the issue solved!
2. Please re-check the ET0_MDC pin, for "_B only" pin group selection; ET0_MDC pin is P401.
3. you can refer to the below app note for debugging ethernet MAC and PHY, refer to section 5 in app-note and can consider ethernet loop-back testing for MAC and PHY to make sure configuration and connection.
RA Ethernet Design and Custom PHY Setup using FSP
ok we will check. We are using mixed pins for ethernet In that case we can use P308 Pin as MDC pin right?
because e2studio does not show any error if we configure mixed pins for ethernet. It is allowing us to configure the P308 for ET0_MDC
Hii Jeyakumar ET0_MDC pin is P401. And also please refer to section 5 of document and debug using logic analyzer.
Thanks. Still, you have not answered why e2studio doesn't show as an error if we configure pin P308 as MDC in Mixed mode. Is it a bug or it is possible?
We also want to know about reset pin configuration in FreeRTOS Aws https example code. Where the Reset sequence of PHY has been configured since we would like to configure P404 as a reset pin for PHY. We are suspecting whether reset sequencing is causing the issue.