I2C SOWP

Hello,

I'm looking in the documentation of RA6M4 to control a good initialization of I2C because after a reset it doesn't return when call to make the first read.

In my code, with FSP 5.5.0, the function iic_master_open_hw_master starts with:

#define IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN           (0x1FU)

static void iic_master_open_hw_master (iic_master_instance_ctrl_t * const p_ctrl, i2c_master_cfg_t const * const p_cfg)
{
    /* Perform IIC reset */
    p_ctrl->p_reg->ICCR1 = (uint8_t) IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN;

But in documentation, about bit SDAO bit and SCLO bit of ICCR1 says:

The SDAO and SCLO bits directly control the SDAn and SCLn signals output from the IIC. When writing to these bits, also
write 0 to the SOWP bit

Why IIC_MASTER_PRV_SCL_SDA_NOT_DRIVEN is 0x1F and not 0x0F?

I think I found a miss in the RA6M3 manual (based in FSP functions) when looking if this doc equals to RA6M4 (my hardware):

The same text miss SCL0:

The SDAO bit directly controls the SDAn and SCLn signals output from the IIC. When writing to these bits, also write 0
to the SOWP bit.

Thanks.