FCL Flash driver for F1KMS4 is not working with IAR compiler

Hello,

If the program runs only with a debugger connected, it may be because of ECC errors. An ECC error can occur when accessing un-initialized parts of RAM. When the debugger is connected RAM is initialized automatically. When there is no debugger, it is recommended to manually initialize RAM. For how to do this please refer below on this article:

en.na4.teamsupport.com/.../19957725

How are other peripherals like CAN and SPI working correctly in this case? We have implemented similar code, but it's still not functioning. Is there any specific configuration required for the FLMD (Flash Mode) pin, or any related setting needed in the IAR environment?

The FLMD0 pin should be high with one of the two following methods:

]Can you share your RAM initialization code ?

Please see it below :

Reference for FLMD0 configuration  #define WRITE_PROTECTED_REG(reg, val) \
(reg) = (val); \
(reg) = (~(val)); \
(reg) = (val);

#define WRITE_FLMDP_REG(reg, val) \
do { \
FLMDPCMD = 0xA5; \
WRITE_PROTECTED_REG(reg, val);\
} while (FLMDPS != 0)

#define FPMON (*(volatile uint8_t *)(0xFFA10000uL))

void Flash_Init(void)
{
volatile r_fcl_status_t fcl_status;

// Step 1: Initialize the Flash Control Library
fcl_status = R_FCL_Init((r_fcl_descriptor_t *)&sampleApp_fclConfig_enu);

if (fcl_status != R_FCL_OK)
{
// Handle initialization error (optional)
return;
}

// Step 2: Set FLMDCNT to 0x01 using protected write to enable Flash Mode
while (FLMDCNT != 0x01)
{
WRITE_FLMDP_REG(FLMDCNT, 0x01);
}

// Step 3: Wait for FWE (Flash Write Enable) bit in FPMON to be set
while ((FPMON & 0x80) == 0)
{
__nop(); // Wait until FWE == 1
}

I do not see any RAM initialization on this code.

Oops, Sorry 

// Define RAM regions to be initialized
#define iRAM_0_START 0xFEDD8000
#define iRAM_0_END   (iRAM_0_START + (32 * 1024) - 1)

#define iRAM_1_START 0xFEDE0000
#define iRAM_1_END   (iRAM_1_START + (128 * 1024) - 1)

#define iRAM_R_START 0xFEE00000
#define iRAM_R_END   (iRAM_R_START + (32 * 1024) - 1)

int __lowinit(void)
{
    volatile unsigned int* p;

    // Initialize Primary RAM (most critical)
    for (p = (unsigned int*)iRAM_1_START; p <= (unsigned int*)iRAM_1_END; p++)
    {
        *p = 0;
    }

    // Optional: Initialize Secondary RAM
    /*
    for (p = (unsigned int*)iRAM_0_START; p <= (unsigned int*)iRAM_0_END; p++)
    {
        *p = 0;
    }
    */

    // Optional: Initialize Retention RAM
    /*
    for (p = (unsigned int*)iRAM_R_START; p <= (unsigned int*)iRAM_R_END; p++)
    {
        *p = 0;
    }
    */

    return 1; // return 1 to continue with normal startup
}

Have you modified the RAM addresses in the code to match those of your device ?

Yes.

Which the part number of your device ?

Which the part number of your device ?

Any update?

I need to know the device you have so I can check the RAM regions in your code.

define region RAM_near = mem:[from 0x00000000 size 0];
define exported symbol _RAM_1ST_BEG = 0xFEEE8000;
define exported symbol _RAM_1ST_END = 0xFEEFFFFF;
define region RAM_1ST_region = mem:[from _RAM_1ST_BEG to _RAM_1ST_END]; // <data default> Global RAM bank A
define exported symbol _RAM_2ND_BEG = 0xFEFE8000;
define exported symbol _RAM_2ND_END = 0xFEFFFFFF;
define region RAM_2ND_region = mem:[from _RAM_2ND_BEG to _RAM_2ND_END]; // SECOND_RAM Global RAM bank B
define exported symbol _RAM_3RD_BEG = _SELF_BEGIN;
define exported symbol _RAM_3RD_END = _SELF_BEGIN + _SELF_SIZE - 1;
define region RAM_3RD_region = mem:[from _RAM_3RD_BEG to _RAM_3RD_END]; // THIRD_RAM Local RAM self/mirror area
define exported symbol _RAM_4TH_BEG = 0x00000000;
define exported symbol _RAM_4TH_END = 0x00000000;
define region RAM_4TH_region = mem:[from 0x00000000 size 0];
define exported symbol _RAM_5TH_BEG = 0x00000000;
define exported symbol _RAM_5TH_END = 0x00000000;
define region RAM_5TH_region = mem:[from 0x00000000 size 0];  Kindly revert if need more information.

I meant to check RAM initialization code. Can you just mention the part number of you device ?