RH850/F1KM-S1_R7F7016894AFP / CLMA3 / how to test clock monitor

I want to handle this part. (5.2.3 Detail of Clock Monitor Control and Test Protection Cluster Registers / 5.2.3.1 ~ 5.2.3.4)

Plz support me. 

Hello,

Clock monitoring is started by the clock monitor when CLMAnCTL0.CLMAnCLME = 1.

The correct write sequence using the CLMAnPCMD register is required in order to update this register.

The writing procedure to write-protected registers is described on chapter 5.1.2:

Thanks~ 

I already know your guide. 

We need CLMA3 GHS/CS+ Based TEST Program as below.

Dear Renesas Expert,

Hello.

Our Customer're trying to implement a specific sequence application utilizing CLMA3 function using RH850F1KM S1 MCU.

1. Separate into application code and bootloader code
2. Activate CLMA3 when initializing application and deactivate when entering bootloader
3. SW Reset when program download is complete

The intention of the scenario is to use CLMA3 in the application area and deactivate it in the bootloader area.

At first,
First of all, in order to use the CLMA3 register, it is judged that the Write Protected sequence must be used to change the register value.
If you could share an example of how to use CLMA3 TEST that includes the code including the Initial Sequence, I think they can use it as a driver for implementing the application.

Please support them.

In addition,
I have checked with TISS.

https://www.renesas.com/en/search?keywords=TN-RH8-B131A%2FE

It seems that there were some issues.

Apart from the above request, has this TISS issue been resolved?

Anyway, looking at the document content in TISS, I can guess that there is an example of a CLMA3 test conducted with the relevant content.

I would appreciate it if you could request the relevant TEST CODE.

Thanks~,

B.R

David.

The official recommendation for the CLMA test (and all FuSa related tests) is provided in the Safety Application Note (SAN) which requires NDA to be in place.  You can submit a private ticket to initiate that process.

The only way to address the issue cited by the technical update via software would be to widen the tolerance on the CLMA configuration.  The TU does not mention how far out of spec the osc operates due to the defect, as such no guess can be made as to how much to widen the test.

The workarounds cite hardware methods to address the issue.  Also mentioned id that if these hardware modifications cannot be implemented to contact Renesas, this would involve another private support ticket.

Hi.

Thanks your advice.

Just.. (without NDA)

First of all, in order to use the CLMA3 register, it is judged that the Write Protected sequence must be used to change the register value.
If you could share an example of how to set CLMA3 Enable/Disable that includes the code including the Initial Sequence Func only,

If we can just provide this initial Func (Write Protected Enable/Disable. Each Func)

They can use it as a driver for implementing the application.

Plz support us. David.

So the issue is how to do the writing procedure to write-protected registers and then enable clock monitoring by writing CLMAnCTL0 register ?

This is quite simple, first they need to follow the steps on 5.1.2 and then write the clock monitor registers of CLM3 accordingly.

Hi.

Thanks your advice.

Question is

'CLMA3 Activation -> CLMA3 Deactivation' (Our customer want to know How to make this sequence by coding)

(CLMA3 Deactivation -> CLMA3 Activation sequence test is OK.)

So, 

We found some comment at UM as below.

Step by Step

\

Therefore,
taking the CAUTION content below as a guide
It is stated that the CLME bit is cleared when the CLMATEST.RESCLM bit is set to 1, which is one of the only conditions for clearing this bit (except AWORES, ISORES)~

We tested this completely.

Thanks~

BR

David.

After the CLMAnCTL0.CLMAnCLME bit is set to 1, writing 0 to this bit is ignored. The only condition for clearing the bit is a reset (AWORES, ISORES). 

If you try to write 0 to this bit while it is 1, CLMAnPRERR bit in CLMAnPS register is set to 1.

So activation -> de-activation sequence is not possible in the way you mean it.

No.
There are two ways.

So I solved it by programming. You can see it above captures.

There are two ways written in UM Caution.
Please read it again carefully~