RL78/G23 Latching Comparator output (with ELCL?) with software reset

Hello,

I am not sure I fully understand the functionality of what you suggest.

Under which conditions should the reset be issued ?

The reset sources are specific but you can issue a software reset (by forcing Internal reset due to illegal-memory access) with code if you need.

Something like the above, with a 'clear' signal (shown as reset in the figure) being issued in software.
Ideally I wouldn't prefer any 1->0->1 transition when a clear signal is issued it the signal is above the reference voltage.
Just to clarify, I do not want to reset the MCU, just reset the latched output of the comparator signal.

The ELCL cannot issue a software reset directly.

The screenshot above is quite similar to the Low-Voltage Detector functionality. An internal reset can be issued if the supply voltage goes beyond a specified level ( VLVD0 or VLVD1 ). But this does not involve detecting voltage from a pin.  Can this work for you ?

Alternatively you can monitor the IVCMP1 and issue the Comparator detection 1 interrupt where you can force a software reset with assembly code: 

// Set illegal instruction to force an internal reset (CC-RL)
.DB 255

Just to clarify, I do not want to reset the MCU, just reset the latched output of the comparator signal

The output pins of the Comparator module are VCOUT0 and VCOUT1.

The comparator outputs are controlled by the Comparator output control register (COMPOCR).

What exactly do you want to reset ?

You can configure COMPOCR so the VCOUTn pins have the Comparator output or the inverted comparator output.

I want to use a latched comparator output to control some external circuitry. I want to use the ELCL to route the comparator output to EO50, potentially using a latch element of the ELCL.

So something like this ?

Thanks, but in that setup I can't see where the latching behaviour from comparator ch1 would come in and also not sure what P11 would connect to.

Can you clarify what you mean by 'latching behaviour' ?

An output that goes high when the analogue input voltage goes above a reference voltage. The output remains high even when the input voltage drops below the reference. An additional software controlled signal can be used to clear the output. Similar to how I attempted to draw in the example. Thanks.