Erase Chip function didn´t erase the hole chip

Hi everyone,

during the unit test, I find out that the erase chip function did not work, correctly. 

I tried both commands 0x60 and 0xC7.

First is wake up chip. Then set write enable. transmit opcode. Read status to check if erase is completed. After each operation the !CS Pin is released. 

When erase is done, i read back every byte from the flash and check if it´s 0xFF.

Page 0 was written before and it´s OK. 

The problem is in the middle and end of the flash memory address room. At the moment at address 0x2FAF8 and  0x7FFEC. This address is not erased, there are still old data.

I try to add a 3 second break between sending opcode and read status back, but it has no effect. 

I also check during the status read, if a protection is active but there is no protection. 

Any Ideas why the data is not erased?

I´m using the AT25SF041B in combination with an STM32G0 prozessor. 

  • Hi,
    First, please clarify a few things:
    1) This happens only on one device or many devices?
    2) Is the issue not erasing only at address 0x2FAF8 and 0x7FFEC? This is consistant on many devices?
    3) Is this repeatable or random?
    4) Have you tried Block Erase commands 20h, 52h, or D8h
    5) Do you have issues with Block Erase commands
    6) What is the clock frequency you use for the SPI?
    7) Does it work better with lower SPI frequency?

    Please verify if you follow the erase procedure:
    1) Send Write Enable command to the device to set the WEL bit of the Status Register to a logical “1” state.
    2) Verify that WEL bit of the Status Register is set to a logical “1” state
    3) The complete opcode 60h or C7h must be clocked into the device before the CS pin is de asserted, and the CS pin must be
    de asserted on an byte boundary (multiples of eight bits); otherwise, no erase is performed.
    4) Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored.
    5) When the CS pin is de asserted, the device erases the entire memory array.
    6) Let the erase be completed. Give it more than 3 seconds before activating CS pin for any read or other operations.
    7) Now, what is the WEL bit of the Status Register read?

    Check if there are glitches with your SPI signals CS, SCK, SI and SO.

    Best regards,
    Renesas Electronics Online Support

  • Hi Sarpa,

    1) I have this problem with 3 devices. 

    2) one device have the problem on both address, and the other two have it only at address 0x7FFEC.

    3) At the moment it is repeatable.

    4) yes i tried on one device without any effect. So at first i was thinking the chip is broken. So i use a other chip. After some testing the new chip had also some data stored i get the problem again.

    5) i don´t think so. 

    6) at the moment it is 0,5MHz

    It looks like the erase is started because the first block is erased. I don´t wait for 3 seconds before i read the status of the chip after starting erasing. But i also try this without a effect. My program is reading the WEL bit after the opcode was transmitted and only give me a "ok" feedback until the WEL bit is low again. 

  • Hi
    For my question: 5) Do you have issues with Block Erase commands;
    you said "5) i don´t think so. ".

    So, if I understand correctly, you do not have issues when Block Erase commands are used to erase.
    The problem is only with Chip Erase commands 0x60 and 0xC7.
    Can you confirm this?

    Specifically, what I am asking is that you try to use Block Erase commands 20h, 52h, or D8h and see it has issues.
    (I know you want to use Chip erase, but this test with Block Erase commands is just to isolate problem areas).

    Best regards,
    Renesas Electronics Online Support

  • Hi,

    today i have test the block erase command. The erase command 0x20, 0x52 and 0xD8 are work and can erase a flash block. 

    Yes the problem is only the command 0x60 & 0xC7.

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