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AT25QF641B Write Enable doesn't set WEL bit in status register

CSTaylorJr

Hi,

I'm working with the AT25QF641B. I can read status registers over the SPI bus, and see that the Quad Enable bit is set in status register 2 (as is expected). However, when I do a write enable (using OP Code 6), I don't see the WEL bit set in subsequent reads of status register 1.

Am I missing a step? Does there need to be some other initialization before the WEL bit can be set?

I have the SPI bus instrumented, and can see the NSS, MISO, and MOSI signals go across. I wasn't able to get a wire stapled to clock.

Any thoughts?

Calvin

  • 0

    Hi Calvin,
    Please follow the following steps to issue the Write Enable command:

    1) The CS pin must first be asserted (LOW).
    2) The opcode of 06h must be clocked into the device (see datasheet page 30 timing).
    3) No address bytes need to be clocked into the device, and any data clocked in after the opcode is ignored.
    4) When the CS pin is de-asserted (HIGH), the WEL bit in the Status Register is set to a logical 1.
    IMPORTANT: The complete opcode must be clocked into the device before the CS pin is de-asserted, and the CS pin must be de-asserted on an byte boundary (multiples of eight bits); otherwise, the device aborts the operation, and the WEL bit state does
    not change.
    5) Please monitor waveforms to make sure you meet these conditions using a scope / logic analyzer.
    6) The AT25QF641B datasheet link =>
    www.renesas.com/.../at25qf641b-datasheet

    Best regards,
    Renesas Electronics Online Support