Dependency between Memory Array Read Latency Cycles vs. Maximum Clock Frequency (with XIP)

Hello everyone,

can someone explain to me how the connection between the latency and the clock frequency in the MRAM M1004204/
M3004204 is?
In the data sheet of the MRAM, reference is made to Tables 22 and 23. Unfortunately, this table only contains the information on the maximum frequencies and latency ranges from min. cycles to max. cycles for the different read types.
Unfortunately, the tables do not show which latency time has to be set, e.g. for a clock frequency of 50 MHz for the Mxxxx2x054xx MRAM or a clock frequency of 80 MHz for Mxxxx2x108xx. The MRAMs are to be operated in (1-1-1) SDR Read Type.