Which bits in the status register of the AT25SF321B are volatile, and which are non-volatile? The datasheet talks about volatile and non-volatile bits, but I can't find a table of which ones are which. In particular, is the Quad Enable bit volatile or non volatile (i.e. does setting it survive a reset)?
Hi Victor,
Non-Volatile Protection feature is explained in the datasheet Table 6 and Table 7 => www.renesas.com/.../at25sf321b-datasheet
The CMP, BP4, BP3, BP2, BP1, and BP0 bits control which portions of the array are protected from erase andprogram operations (see Table 6 and Table 7).Please see the datasheet page 42 for details => www.renesas.com/.../at25sf321b-datasheet
Best regards,Renesas Electronics Online Support
I'm asking about whether the status register itself (or parts of it) are non-volatile. In particular, the Quad Enable bit. In my testing, if I set the Quad Enable bit, then reset the device, the Quad Enable bit is still set (i.e. it is non-volatile), but I can't find a description of this behaviour in the datasheet.
Hi,The Write Status Register (01h) is for non volatile status register.It is explained under section 11.2.So, when you use this command to set The Quad Enable bit, it is non volatile.
There is also a Volatile version of the Status Register. Actually, during power up reset, the non-volatile Status Register bits (described under section 11.2) are copied to a volatile version of the Status Register that is used during device operation.This gives more flexibility to change the system configuration and memory protection schemes quickly withoutwaiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatilebits.
Volatile version of the Status Register is explained under section 11.3 of the datasheet. For volatile version, the Write Enable for Volatile Status Register (50h) is used.