I have an existing circuit using a PIC32 and a dual port RAM (IDT 7134), I switch to the 70V06L to get a 3v3 system, using the same address lines (+2) and IO port. I have the same signal (OE / WR / CE) going to the device. I connected the SEM to VCC. For this test, I am only using the right side, writing/reading to the same address (first 10 bytes) . But I cannot seem to be able to write to the chip. When I read, I have garbled data, but that might just be the state of the memory. If I set CE to HIGH, I do get high impedance output and read FF on the IO port. I scoped all my signals and put large delays on read and write and I cannot see why the data does not get to (or is miss read from) the device. If I switch to the the 7134, the cycles works, even at 3v3 signal levels. I am sure I am missing something (I have 10 devices, I checked with 3 and they all behave the same),
I rewrote the code to manually control the control lines, so I can easily see the OER and WR signals (I was using a parallel port controller but I was not sure if that worked properly).
*Edit: When the data is read, the data i not what I wrote, but it is consistent. If I read the full memory, then power cycle the device, I read the same data (same without power cycle), so the read data is not random, just not what I wrote there.
The circuit is pretty simple, direct IO from the micro to the 70v06 25LPG, no pull up/down (internal weak pull up only, PIC32MZ795F512L
Code to Write:
UINT16 i = 0; PORTS_DATA_MASK dataMask = (PORTS_DATA_MASK)0x00FF;
// Ensure the device is in high impedance mode SetPin(PMWR); SetPin(PMRD); ClearPin(PMCS1);
// Set the channel E to output PLIB_PORTS_DirectionOutputSet(PORTS_ID_0 , PORT_CHANNEL_E, dataMask);
for (i = 0; i < aSize; i ++){ // Set the address SetSharedRamMemory(aSRamWriteAddress + i); // Set the bus value PORTE = pData[i]; // Arm the write function ClearPin(PMWR); ShortDelay(1); // Adjusted to debug // Memory will be stored on raising edge if the PMWR signal SetPin(PMWR); }
SetPin(PMCS1);}
Code to Read:
{ UINT16 i = 0;
PORTS_DATA_MASK dataMask = (PORTS_DATA_MASK)0x00FF;
// Set the memory device to high impedance SetPin(PMWR); SetPin(PMRD); ClearPin(PMCS1);
// Set the channel E as an input PLIB_PORTS_DirectionInputSet(PORTS_ID_0 , PORT_CHANNEL_E, dataMask);
for (i = 0; i < aSize; i ++){ // Set the address SetSharedRamMemory(aSRamReadAddress + i); // Ask for the data at that address ClearPin(PMRD); // give the chip some time to put the data on the bus ShortDelay(1); // Read the bus pData[i] = PORTE; // Go back to high impedance SetPin(PMRD); }
Any pointer would be helpful as I am pulling the rest of my hair off
The issue was the master line. I had it on the 3v3 on my drawing, but the gerber was left opened. This line must be driven to allow writes to the device