Hello, during a burst read, if i hold SCLK low, and then re-start clocking 'x cycles' later will that cause any issues with auto-reading out the entire memory array using Quad SPI mode?
Hi There,Thank you for posting your question online.Could you please share the exact Part Number you are working with?Best Regards,OV_Renesas
Thanks for the quick reply, we haven't chosen a part yet as this is a new product, but something like "AT25QF128A' is what we have in mind.
Hi There,Thank you for the reply.
jonrosea said: during a burst read, if i hold SCLK low, and then re-start clocking 'x cycles' later will that cause any issues with auto-reading out the entire memory array using Quad SPI mode?
Please refer on the AT25QF128A Datasheet, And Section 8.2 Read Commands, on page: 23It would not be suggested to explicitly hold the SCLK to LOW. The Serial Clock provides the synchronization reference for the SPI interface, by keeping it Low it will make the SPI driver and the AT25 NOR Flash to not work as expected.Best Regards,OV_Renesas
If I am using Quad mode, such that no 'hold' pin is available....is there a way to pause reading without starting the read cycle over again?
Hi John,Thank you for the reply and apologies for the delay.We are looking into this and we will get back to you as soon as possible.Best Regards,Orestis