AT25SF041B : Block Erase Time after 500 Cycles - Temperature Influence?

Hi Ralf,

Thank you for posting your question online.
Let me check on this with the Memories team and I will get back to you as soon as possible.

Best Regards,
OV_Renesas

Hi Ralf,

We need more information about your test:
In the test did you erase every and program each and every 4K block in the memory array in each of the 500 test cycles?
Did you do continouosly?

Best Regards,
OV_Renesas

Hello OV,

in the time of 40days every 2 hours one 4k block was erased and in another 4k Block the data was stored. In the next 2 hour cycle the before erased block is programmed and the other block is erased. In fact this means that one block only get 240 erase cycles. The reason for this alternating erase / write cycles is to enable a quick programming.

best regards

          Rastarmann

Hi Rastarmann,

Thank you for the reply and apologies for the delay.
The Memories Support Team would like to verify the following:

• The test included 480 cycles.
• A new cycle started 2 hours after the previous cycle.
• Therefore total test time was 960 hours which is 40 days.
• In every even text cycle block A was erased and block B was programmed. In every odd test cycle block A was programmed and block B was erased. It was a "ping-pong" between A and B.
• No other block was touched in the test, only the two blocks A and B.

Best Regards,
OV_Renesas

That is right.

Hi Rastarmann,

Erase time of 600ms is not reasonable after 240 erase cycles and 240 programming cycles. It is definitely excessive and by a lot.
According to the datasheet the max value of 4K block erase time is 200ms which was measured after 100K cycles.
A temperature of 50C may contribute but we think its impact its negligible.
We will consult with product engineering (PE. But we also have more questions:

• How many parts were tested?
• What is the full part#? (we want to know the package type).
• Can they provide date code(s)? They show up on the chip label in YYWW format (YY = year, WW = work week)
• How was erase time measured? We know it's pretty obvious but we would like to hear details from you to make sure.
  
  
  

Best Regards,
OV_Renesas

Hello Renesas Team,

here the answers to yourquestions:

- In the endurance test we had over 25 parts . In all parts we had an excessive increase of the erase time.

- In our system I found the order No. "AT25SF041B-MAHD-T"

- Unfortunally I dont have the data codes from the production

- Our firmware was modified in a way, that the status register was checked after the erase command.

   It was measured the time when the memory is available again.

   (In our standard firmware the status register was not checked as the memory is only read out in a cycle 
     of 500ms)

But I also have some more questions:

- I understood that the erase time of 200 ms is at the end of the life time.  In which range should be the erase time of a new memory ?

- Do read cycles also contibute to the degeneration of the memory ?

Thanks for your support!

Best regards

      Ralf

Hi Ralf,

Thank you for the reply.
We repeated your experiment, except we did not wait 2 hours between cycles. All 480 cycles (240 erase + 240 program for each of the blocks) were executed continuously. This puts a lot more stress on the flash compared to your experiment. 
We did not run the experiment at 50C. The temperature of 50C is nothing for flash and we do not believe it will make a difference.
We choose block A to be at address 0x10000 and block B to be at address 0x11000. The erase times were much lower than the datasheet typical. They were mostly under 30ms, sometimes a little above. And during the 480 cycles we did not see a significant change in the erase time.
Please find attached a spreadsheet which shows erase time for block A and block B in each cycle. Time is expressed in microseconds.
It seems likely that you are doing something wrong in your side, either the temperature is much higher, the number of cycles is much higher than described or something else.
Please share with us what is the flash Vcc (supply votlage) used in your system.
To answer your questions as well:

Rastarmann said:

- I understood that the erase time of 200 ms is at the end of the life time.  In which range should be the erase time of a new memory ?

Yes, 200ms is a number of device that reached the end of the endurance test per the datasheet and JEDEC endurance testing standard. An example of fresh part erase time can be seen in the attached spreadsheet. Officially, it is 60ms per datasheet typical value but you will find many flash part under that.

Rastarmann said:

- Do read cycles also contibute to the degeneration of the memory ?

Read cycles should not contribute much to erase time.
AT25SF041B-480-PE-cycle-test.xlsx
Best Regards,
OV_Renesas

Hi Ralf,

As requested earlier we would like to know the flash Vcc value.
Additionally, we would like to confirm again that in each of the 480 cycles block A is erase once and block B is programmed once (or vice versa)? We started thinking maybe this is a misunderstanding and perhaps you perform erase/program many times in each cycle.
Do you have a log indicating how the erase times changes from cycle to cycle? Similar to the spreadsheet we shared?

Best Regards,
OV_Renesas

Hello OV,

thanks for your measurements! 

The flash is supplied with 3,2V. There is no misunderstanding. You got it right.

We monitored the SPI Bus with a logic analyzer over 2 days. We did not find additional erase cycles so far. 

We did not measure the erase time over the lifetime continously. But we have the following data of some samples. 

It is interesting , that the erase time increased even after one week.

At the moment we check, if a glue that is applied on the chip could have bad influence to the memory.

   best regards

        Ralf