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Programming RZ/A1M with dual quad spi and J-link

Muco

Hello All,

I'm trying to get a Renesas RZ/A1M working with dual quad spi flash chips.

The first problem is that J-link (v6.41a beta) doesn't support the RZ/A1M (R7S721010VC). So i tried to program as a RZ/A1H (the bigger brother of the RZ/A1M).

The bootloader (a modified version of the Stream-it! V2 bootloader) is programmed and running in the RZ/A1M, so far so good.

The next step is to program the user application. The programming (and verifying) is successful, however the code is NOT running. I can see why, the string ".BootLoad_ValidProgramTest." is garbled, it reads ". o t o d V l d r g a T s ." from the bootloader point of view. This suggests the 2nd quad spi flash is not working. When I use a scope I actually don't see data on any of the spi data pins (clock and chip select work).

Next I monitored the same pins while programming the RZ/A1M and to my great surprise I didn't see any data!

So programming and verifying with a J-link debug probe works, but reading back by the RZ/A1M doesn't work. It is a mystery to me what is happening here. Say all data is programmed in the 1st quad flash chip (what the scope suggests because I don't see any data on the 2nd quad spi flash chip) I would expect the string to read ". B o o t L o a d _ V a l i" from the bootloader point of view.

Can someone tell me how to procede?

My setup is a follows:

1x RZ/A1M (R7S721010VC)

2x Quad SPI Flash MX25L51245GMI

SPBCLK_0 -> P9.02

SPBSSL_0 -> P9.03

SPBIO00_0 -> P9.04

SPBIO10_0 -> P9.05

SPBIO20_0 -> P9.06

SPBIO30_0 -> P9.07

SPBIO01_0 -> P8.14

SPBIO11_0 -> P8.15

SPBIO21_0 - P9.0

SPBIO31_0 - P9.1

 

J-link batch file:

@echo off

set DEVICE=R7S721000_DUALSPI
set BASE=C:\Program Files (x86)\SEGGER\JLink_V641a\

"%BASE%\JLink.exe" -if JTAG -speed 12000 -device %DEVICE% -jtagconf -1,-1 -CommandFile application-apiqe-wr.jlink

pause

 

J-link command file:

r
h

// Set P8.14 .. P8.15 as alternate function 2.
w2 0xFCFE3420, 0xC000 // PMC8
w2 0xFCFE3A20, 0x0000 // PFCAE8
w2 0xFCFE3620, 0x0000 // PFCE8
w2 0xFCFE3520, 0xC000 // PFC8
w2 0xFCFE7220, 0xC000 // PIPC8

// Set P9.0 .. P9.7 as alternate function 2.
w2 0xFCFE3424, 0x00FF // PMC9
w2 0xFCFE3A24, 0x0000 // PFCAE9
w2 0xFCFE3624, 0x0000 // PFCE9
w2 0xFCFE3524, 0x00FF // PFC9
w2 0xFCFE7224, 0x00FF // PIPC9

// Configure SPI Multi I/O Bus Controller.
w4 0x3FEFA000, 0x01AA5001 // CMNCR_0
w4 0x3FEFA010, 0x00030000 // DRCMR_0
w4 0x3FEFA01C, 0x00004700 // DRENR_0
w4 0x3FEFA00C, 0x00000000 // DRCR_0
w4 0x3FEFA014, 0x00000000 // DREAR_0
w4 0x3FEFA008, 0x00000003 // SPBCR_0

loadbin .\RZA1LU_Sample\HardwareDebug\RZA1LU_Sample.bin,0x18080000
verifybin .\RZA1LU_Sample\HardwareDebug\RZA1LU_Sample.bin,0x18080000

r
g
q

 

I tried with and without additional "wx" commands but both to no avail.

Tia.

  • The first problem is that J-link (v6.41a beta) doesn't support the RZ/A1M (R7S721010VC). So i tried to program as a RZ/A1H (the bigger brother of the RZ/A1M).

    RZ/A1H and RZ/A1M are the same device...just with different amount of internal RAM.

     

    For Jlink, I've always used "-device R7S721001_DualSPI" when programming dual SPI flash. you have "R7S721000_DUALSPI" (dual is all capitals). I'm not sure if Jlink is case sensitive or not.

     

    You do not have to set up the pins for J-Link in your programming script. The J-Link firmware will do that for your automatically.

    However, I think that might be your issue.

    Jlink assumes the 2nd QSPI is on P2_12/13/14/15 and configures those pins before programming.

    But your 2nd QSPI is on P8_14/P8_15/P9_0/P9_1.

    You might have to contact Segger and ask them if how you are doing it is the correct way or not.

  • in reply to Chris
    Hi,

    I connected a 3rd flash chip on pins P2_12 to P2_15 but I still don't see any sign of life on the flash chip (measured ports P8_14, 15 P9_0, 1 and P2_12 to P2_15 with a scope).

    I suspect only 1 flash chip is used with this microcontroller even in DualSPI mode.

    Chris, I use a PLQP0256LB-A version of the chip, so the bigger brother of the R7S721010VC is the R7S721000VC, not the R7S721001VC !

    I will ask Segger how they imagine to connect the 2nd quad spi flash chip.

    With kind regards,
    Muco
  • in reply to Muco

    When you pass   -device R7S721001_DualSPI  on the command line of the Segger J-Link tool, it will program both SPI flashes. You should see data communications on both QSPI#0 data lines (P9_4,5,6,7) and QSPI#1 data lines (P2_12,13,14,15).

    You do not see data when you provide -device R7S721001_DualSPI  on the command line???

     

    Chris, I use a PLQP0256LB-A version of the chip, so the bigger brother of the R7S721010VC is the R7S721000VC, not the R7S721001VC !

    Don't worry about the name passed to J-Link. There is only 1 device 'name' for J-Link for all RZ/A.

    When J-Link connects, it reads a register in the RZ/A that will tell it what type of device it is (RZ/A1L, RZ/A1LU, RZ/A1M, RZ/A1H).

    Chris

  • in reply to Chris

    Hi,

    Unfortunately I don't see data on pins P2_12,13,14,15. The jlink silently programs everything in 1 flash chip without giving an error about not finding the 2nd flash chip (even with the device R7S721001_DualSPI). The bootloader is configured in single spi flash chip mode and is booting the application.

    I'm still not convinced the jlink supports the RZ/A1M see attached picture of supported RZ mcu's.

  • in reply to Muco

    Hi Muco,

    I do not know if your board works correctly, I guess to check operation
    with internal-RAM-based u-boot.

    1. Restored the original board version
    2. Create the u-boot that runs on RZ/A1M internal RAM
    3. Download the u-boot with J-Link and exeute it
    4. Check if u-boot can access Dual QSPI flash or not

    I believe that your u-boot will be able to access the second flash chip.

    By the way, you said:
    > I connected a 3rd flash chip on pins P2_12 to P2_15 but I still don't see
    > any sign of life on the flash chip (measured ports P8_14, 15 P9_0, 1
    > and P2_12 to P2_15 with a scope).

    How did you handle the SPBCLK_0 (P9_2) and SPBSSL_0 (P9_3) signals?
    Needless to say, these clock and control signals should be connected to
    the second flash chip (that you call it the 3rd flash chip).

    Best regards,

  • in reply to Pecteilis
    Hi Pecteilis,

    Thanks for your reply.
    At this moment I have 3 flash chips connected to the RZ just to see if I can get it to work.
    The clock / slave select are connected to all 3 spi flash chips. For clarification the 2nd and 3rd flash are connected to P8_14, 15 P9_0, 1 and P2_12 to P2_15.

    u-boot sounds like Linux. I don't know anything about Linux (and want to keep it that way :) ).

    With kind regards,
    Muco.
  • in reply to Muco
    Hello,

    I tried to connect the 2nd flash chip again on port pins P2_12 to P2_15 and this time it works!
    It was probably a combination of a soldering issue and measurement mistake.

    Last time I probed P2_15 cause that pin was physically easy to measure on, but it seems J-Link programs the flash chips in 1bit mode (so only MISO/MOSI). This time is do see data on P2_12/P2_13.

    This issue is solved.

    Thanks all.