Hi All, We are working rzg2n based customized board,we got uboot working. Our hard ware voltage for SDIO interface is 1.8V fixed. when we try to detect micro-sd card
it is showing below error.
U-Boot 2018.09 (Feb 06 2023 - 11:03:23 +0000)
CPU: Renesas Electronics R8A774B1 rev 1.1Model: Relysys Technologies Relysys RZ/G2N platform (relysys-rzg2n)DRAM: 1.9 GiBBank #0: 0x048000000 - 0x0bfffffff, 1.9 GiB
Watchdog: Not found by seq!WDT: watchdog@e6020000Watchdog: Started!MMC: sd@ee140000: 0, sd@ee160000: 1Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@e6e88000Out: serial@e6e88000Err: serial@e6e88000Net: eth-1: ethernet@e6800000Hit any key to stop autoboot: 0=>=>=> mmc infoCard did not respond to voltage select!
Please help us to how to set microsd card voltage to 1.8v in software and get it work,
Thanks and regards,
Nagaraja
Linux kernel programming said:Card did not respond to voltage select!
That message means it cannot talk to the SD card at all. The first thing u-boot does is try to read the voltage select registers, so it is failing on the first SD card command.
Put a scope on the pins and see what is coming out.
Hi Chris,
Thanks for reply, The SD card is working now as below
==========================================
[ 0.000144] NOTICE: BL2: RZ G2N Initial Program Loader(CA57)
[ 0.004408] NOTICE: BL2: Initial Program Loader(Rev.2.0.6)
[ 0.009941] NOTICE: BL2: PRR is RZG G2N Ver.1.1
[ 0.014524] NOTICE: BL2: Board is Relysys RZ/G2N Rev.4.0
[ 0.019875] NOTICE: BL2: Boot device is QSPI Flash(40MHz)
[ 0.025315] NOTICE: BL2: LCM state is CM
[ 0.029295] NOTICE: BL2: DDR3200(rev.0.40)
[ 0.036255] NOTICE: BL2: [COLD_BOOT]
[ 0.040308] NOTICE: BL2: DRAM Split is OFF
[ 0.043003] NOTICE: BL2: QoS is default setting(rev.0.09)
[ 0.048446] NOTICE: BL2: DRAM refresh interval 1.95 usec
[ 0.053803] NOTICE: BL2: Periodic Write DQ Training
[ 0.058830] NOTICE: BL2: Lossy Decomp areas
[ 0.062962] NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
[ 0.070046] NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
[ 0.076958] NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
[ 0.083873] NOTICE: BL2: v1.5(release):af9f429-dirty
[ 0.088881] NOTICE: BL2: Built : 11:02:14, Feb 6 2023
[ 0.094069] NOTICE: BL2: Normal boot
[ 0.097708] NOTICE: BL2: dst=0xe6321100 src=0x8180000 len=512(0x200)
[ 0.104197] NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
[ 0.111934] NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=65536(0x10000)
[ 0.130836] NOTICE: BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000)
[ 0.351082] NOTICE: BL2: Booting BL31
U-Boot 2018.09 (Feb 09 2023 - 07:02:07 +0000)
CPU: Renesas Electronics R8A774B1 rev 1.1
Model: Hoperun Technology HiHope RZ/G2N platform (hihope-rzg2n)
DRAM: 3.9 GiB
Bank #0: 0x048000000 - 0x0bfffffff, 1.9 GiB
Bank #1: 0x480000000 - 0x4ffffffff, 2 GiB
Watchdog: Not found by seq!
WDT: watchdog@00000000e6020000
Watchdog: Started!
MMC: sd@ee100000: 0, sd@ee160000: 1
Loading Environment from MMC... *** Warning - bad CRC, using default environment
In: serial@e6e88000
Out: serial@e6e88000
Err: serial@e6e88000
Net: eth-1: ethernet@e6800000
Hit any key to stop autoboot: 0
=> mmc dev 0
switch to partitions #0, OK
mmc0 is current device
=> setenv bootargs root=/dev/mmcblk1p2
=> setenv bootcmd "fatload mmc 0:1 0x48080000 Image; fatload mmc 0:1 0x48000000 Image-r8a774b1-hihope-rzg2n-ex.dtb; booti 0x48080000 - 0x48000000"
=> boot
14522880 bytes read in 605 ms (22.9 MiB/s)
58124 bytes read in 5 ms (11.1 MiB/s)
## Flattened Device Tree blob at 48000000
Booting using the fdt blob at 0x48000000
Using Device Tree in place at 0000000048000000, end 000000004801130b
Starting kernel ...
Please help us to fix this problem.
Thanks and regads,
That looks OK to me.
Try adding the parameter 'earlycon' to the bootargs to see if anything prints out
You will also want to add 'bootwait' too since you might hit that issue next.
Thanks for the reply , we got Micro-SD card working . Now we are facing the LPDDR SIZE issue , we are using SDK-1.0.6 and using 4GB :MT53E1G32D2FW-046 WT:A(Micron),
We canfigured LPDDR SIZE as 4GB both in u-boot and kernel dts file but we are facing the below issue:
memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; };
memory@480000000 { device_type = "memory"; reg = <0x4 0x80000000 0x0 0x80000000>; };
when we configured RAM size as 2GB ,both u-boot and kernel works fine,but when we configured RAM size as 4GB u-boot works but we are not able to write 480000000 and kernel stops stops at
booting kernel....................
We are taken RZG2N-hihope as reference and working on custom made RZG2N board.
We are not able to get 4GB Micron chip working , could you please guide us what are we missing here.
How do we go about getting 4GB working on our board.
Nagaraja.
Type bdinfo in u-boot and paste the result here.
Hi MicBis,
Please find the output of bdinfo in below attached image.
Thanks & Regards
Mahesh R
Have you verified that the entire 4GB DDR is working in Flash Writer?
we have changed the DDR density in ddr_b/boot_init_config.c
{0x04 0xFF} is working
but changing it to {0x04 0x04} is not working
so we are able to write only first 2GB.
I can't find the DS of the MT53E1G32D2FW-046, anyway to have 4GB the RZ/G2N only supports 2-rank LPDDR4, 16Gbit x 2, 4GB per channel (only 1 channel is available), corresponding to 0x4, 0x4 setting.
This is what I would check.
Dear Renesas Team,
Please find the MT53E1G32D2FW-046 datasheet.
0412.MT53E1G32D2FW 046.pdf
4213.MT53E1G32D2FW 046.pdf
That part looks OK to me.
Is your design 100% the same as the hihope board?
Again, have you tested the DDR using Flash Writer?
Yes have taken the same reference as the RZ/G2N Hi-hope board.
Yes in Flash writer if we enable 4GB configuration i.e as below
{0x04 0x04} in ddr_b/boot_init_config.c file
then we are able to see junk messages printed on the minicom screen as below
Fullscreen 4GB_DDR(0x04,0x04).txt Download - Load Program to SystemRAM --------------- please send ! initram.... 2nd rank.... start.... init ddr.... init ddr....1 init ddr....2 init ddr....3 init ddr....4 init ddr....5 init ddr....6 init ddr....7 init ddr....7.1 init ddr....7.2 init ddr....7.3 init ddr....7.4 init ddr....7.5 init ddr....7.6 init ddr....7.6.2 init ddr....7.6.3 init ddr....7.6.4 init ddr....7.6.5 init ddr....7.6.6 init ddr....7.6.7 init ddr....7.7 init ddr....7.7 %d init ddr....7.8 InitDram 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please find the attached schematic.
LPDDR4.pdf
please help us to sort out the issue.
Your schematics look ok to me. I assume Channel 1 signals are going nowhere.
What do the number represent in you log? What is the step that fails?It is weird that you get junk characters, that code runs out of internal SRAM.
Hi Linux kernel programming (Nagaraja),
May I know how did you resolve SD card not detected issue? We are also facing same problem on our G2M design. Appreciate your help here.
Regards,
Dipen Patel
Hi MIcBIs,
Those are the line we put in boot_init_dram_Config-preset.c in the flash_writer code for debug purpose
Could you please let us know is Renesas SDK suports memory controller complaiance to both JESD209-4A and JESD209-4B specification on RZG2N Evaluation platform.
or it supports only JESD209-4A.
For your reference we are attaching the image of the processor which we are using
Nagraja.
I would suggest to get in touch with your local Renesas sales / support for this kind of questions.
What spec addition of JESD209-4B are you after?
Micron guys are saying JESD209-4A version of LPDDR4 is 16 bit row address
and JESD209-4B is version of LPDDR4 is 17 bit row address.
So we want to know is our RZG2N support either of one or both.
Hi MIcBis,
Please find the attached data sheet of the LPDDR that we are useing , only difference is the row address is R[16:0] .
And only One rank
200b_z32m_sdp_ddp_qdp_auto_lpddr4_lpddr4x (1).pdf
Thanks and regards
This 1-rank memory cannot work with RZ/G2N, as I mentioned:
MicBis said:I can't find the DS of the MT53E1G32D2FW-046, anyway to have 4GB the RZ/G2N only supports 2-rank LPDDR4, 16Gbit x 2, 4GB per channel (only 1 channel is available), corresponding to 0x4, 0x4 setting.
The other DS included different information.