P24 bank pins configuration issue in RZ-FIVE

Hello,

We are configuring P24 bank pins for below interfaces and below is the dts configurations for the same.

SCIF4:
TX: P24_5 ALT5
RX: P24_4 ALT5
Below is the dts pinmux configuration:
scif4_pins: scif4 {
pinmux = <RZG2L_PORT_PINMUX(24, 5, 5)>, /* TxD */
<RZG2L_PORT_PINMUX(24, 4, 5)>; /* RxD */
};

CAN_B:
TX: P24_2 ALT1
RX: P24_3 ALT1
Below is the dts pinmux configuration:
canfd1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(24, 2, 1)>, /* TX */
<RZG2L_PORT_PINMUX(24, 3, 1)>; /* RX */
};

PWM (MTIOC4D):
MTI0C4D: P24_0 Alt3
Below is the dts pinmux configuration:
mtu3_pins: mtu3 {
pinmux = <RZG2L_PORT_PINMUX(17, 0, 4)>; /* MTIOC3A */
<RZG2L_PORT_PINMUX(24, 0, 3)>; /* MTI0C4D */
};


While booting we get errors as shown below.

[ 0.888759] pinctrl-rzg2l 11030000.pin-controller: pin 197 is not registered so it cannot be requested
[ 0.898082] pinctrl-rzg2l 11030000.pin-controller: pin-197 (1004c800.serial) status -22
[ 0.906071] pinctrl-rzg2l 11030000.pin-controller: could not request pin 197 (non-existing) from group scif4 on device pinctrl-rzg2l
[ 0.955656] pinctrl-rzg2l 11030000.pin-controller: pin 194 is not registered so it cannot be requested
[ 0.964975] pinctrl-rzg2l 11030000.pin-controller: pin-194 (10050000.can) status -22
[ 0.972705] pinctrl-rzg2l 11030000.pin-controller: could not request pin 194 (non-existing) from group can1 on device pinctrl-rzg2l
[ 1.539777] pinctrl-rzg2l 11030000.pin-controller: pin 192 is not registered so it cannot be requested
[ 1.556594] pinctrl-rzg2l 11030000.pin-controller: pin-192 (10001200.timer) status -22
[ 1.564530] pinctrl-rzg2l 11030000.pin-controller: could not request pin 192 (non-existing) from group mtu3 on device pinctrl-rzg2l


Is there any limitation in BSP, so that we are not able to use the P24 bank pins?

Regards.

Parents
  • This is interesting, P24_x  with x>=2 do not exist in RZ/G2L. Is P24_0 or P24_1 ok?

  • Hello,

    P24_0 with ALT3 we are using like below and it is not working.

    P24_0 with ALT3 we are using for PWM (MTIOC4D). Below is the dts configuration.
    mtu3_pins: mtu3 {
    pinmux = <RZG2L_PORT_PINMUX(17, 0, 4)>; /* MTIOC3A */
    <RZG2L_PORT_PINMUX(24, 0, 3)>; /* MTI0C4D */
    };

    Below is the error prints observed while booting.
    [ 1.539777] pinctrl-rzg2l 11030000.pin-controller: pin 192 is not registered so it cannot be requested
    [ 1.556594] pinctrl-rzg2l 11030000.pin-controller: pin-192 (10001200.timer) status -22
    [ 1.564530] pinctrl-rzg2l 11030000.pin-controller: could not request pin 192 (non-existing) from group mtu3 on device pinctrl-rzg2l

  • P19_1..P25_1 are additional pins available in RZ/five only.
    To be more precise, the pins are available in RZ/G2UL as well but they have a fixed functionality.

    I suspect there's something to be adjusted in the pin controller driver.

  • Hello,

    We are using RZ-FIVE only.
    In pin control driver accessing of P0 to P18 is configured.
    How to add support for accessing of P19 to P25 for RZ-FIVE in pin control driver?

  • Hello,

    We are not able to open the link which you shared. 

    Kindly share again.

  • fix_non-dedicated_rzfive_pins.patch.txt
    diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    index 4b7d569b3464..c40239709c7d 100644
    --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    @@ -237,6 +237,58 @@ static const int rzg2ul_pin_info[] = {
     	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
     };
     
    +static const int rzfive_pin_info[] = {
    +	RZG2L_PIN_INFO(0,  0), RZG2L_PIN_INFO(0,  1), RZG2L_PIN_INFO(0,  2),
    +	RZG2L_PIN_INFO(0,  3),
    +	RZG2L_PIN_INFO(1,  0), RZG2L_PIN_INFO(1,  1), RZG2L_PIN_INFO(1,  2),
    +	RZG2L_PIN_INFO(1,  3), RZG2L_PIN_INFO(1,  4),
    +	RZG2L_PIN_INFO(2,  0), RZG2L_PIN_INFO(2,  1), RZG2L_PIN_INFO(2,  2),
    +	RZG2L_PIN_INFO(2,  3),
    +	RZG2L_PIN_INFO(3,  0), RZG2L_PIN_INFO(3,  1), RZG2L_PIN_INFO(3,  2),
    +	RZG2L_PIN_INFO(3,  3),
    +	RZG2L_PIN_INFO(4,  0), RZG2L_PIN_INFO(4,  1), RZG2L_PIN_INFO(4,  2),
    +	RZG2L_PIN_INFO(4,  3), RZG2L_PIN_INFO(4,  4), RZG2L_PIN_INFO(4,  5),
    +	RZG2L_PIN_INFO(5,  0), RZG2L_PIN_INFO(5,  1), RZG2L_PIN_INFO(5,  2),
    +	RZG2L_PIN_INFO(5,  3), RZG2L_PIN_INFO(5,  4),
    +	RZG2L_PIN_INFO(6,  0), RZG2L_PIN_INFO(6,  1), RZG2L_PIN_INFO(6,  2),
    +	RZG2L_PIN_INFO(6,  3), RZG2L_PIN_INFO(6,  4),
    +	RZG2L_PIN_INFO(7,  0), RZG2L_PIN_INFO(7,  1), RZG2L_PIN_INFO(7,  2),
    +	RZG2L_PIN_INFO(7,  3), RZG2L_PIN_INFO(7,  4),
    +	RZG2L_PIN_INFO(8,  0), RZG2L_PIN_INFO(8,  1), RZG2L_PIN_INFO(8,  2),
    +	RZG2L_PIN_INFO(8,  3), RZG2L_PIN_INFO(8,  4),
    +	RZG2L_PIN_INFO(9,  0), RZG2L_PIN_INFO(9,  1), RZG2L_PIN_INFO(9,  2),
    +	RZG2L_PIN_INFO(9,  3),
    +	RZG2L_PIN_INFO(10, 0), RZG2L_PIN_INFO(10, 1), RZG2L_PIN_INFO(10, 2),
    +	RZG2L_PIN_INFO(10, 3), RZG2L_PIN_INFO(10, 4),
    +	RZG2L_PIN_INFO(11, 0), RZG2L_PIN_INFO(11, 1), RZG2L_PIN_INFO(11, 2),
    +	RZG2L_PIN_INFO(11, 3),
    +	RZG2L_PIN_INFO(12, 0), RZG2L_PIN_INFO(12, 1),
    +	RZG2L_PIN_INFO(13, 0), RZG2L_PIN_INFO(13, 1), RZG2L_PIN_INFO(13, 2),
    +	RZG2L_PIN_INFO(13, 3), RZG2L_PIN_INFO(13, 4),
    +	RZG2L_PIN_INFO(14, 0), RZG2L_PIN_INFO(14, 1), RZG2L_PIN_INFO(14, 2),
    +	RZG2L_PIN_INFO(15, 0), RZG2L_PIN_INFO(15, 1), RZG2L_PIN_INFO(15, 2),
    +	RZG2L_PIN_INFO(15, 3),
    +	RZG2L_PIN_INFO(16, 0), RZG2L_PIN_INFO(16, 1),
    +	RZG2L_PIN_INFO(17, 0), RZG2L_PIN_INFO(17, 1), RZG2L_PIN_INFO(17, 2),
    +	RZG2L_PIN_INFO(17, 3),
    +	RZG2L_PIN_INFO(18, 0), RZG2L_PIN_INFO(18, 1), RZG2L_PIN_INFO(18, 2),
    +	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
    +	RZG2L_PIN_INFO(19, 0), RZG2L_PIN_INFO(19, 1), RZG2L_PIN_INFO(19, 2),
    +	RZG2L_PIN_INFO(20, 0), RZG2L_PIN_INFO(20, 1), RZG2L_PIN_INFO(20, 2),
    +	RZG2L_PIN_INFO(20, 3), RZG2L_PIN_INFO(20, 4), RZG2L_PIN_INFO(20, 5),
    +	RZG2L_PIN_INFO(20, 6), RZG2L_PIN_INFO(20, 7),
    +	RZG2L_PIN_INFO(21, 0), RZG2L_PIN_INFO(21, 1),
    +	RZG2L_PIN_INFO(22, 0), RZG2L_PIN_INFO(22, 1), RZG2L_PIN_INFO(22, 2),
    +	RZG2L_PIN_INFO(22, 3),
    +	RZG2L_PIN_INFO(23, 0), RZG2L_PIN_INFO(23, 1), RZG2L_PIN_INFO(23, 2),
    +	RZG2L_PIN_INFO(23, 3), RZG2L_PIN_INFO(23, 4), RZG2L_PIN_INFO(23, 5),
    +	RZG2L_PIN_INFO(24, 0), RZG2L_PIN_INFO(24, 1), RZG2L_PIN_INFO(24, 2),
    +	RZG2L_PIN_INFO(24, 3), RZG2L_PIN_INFO(24, 4), RZG2L_PIN_INFO(24, 5),
    +	RZG2L_PIN_INFO(25, 0), RZG2L_PIN_INFO(25, 1),
    +	RZG2L_PIN_INFO(28, 0), RZG2L_PIN_INFO(28, 1), RZG2L_PIN_INFO(28, 2),
    +	RZG2L_PIN_INFO(28, 3), RZG2L_PIN_INFO(28, 4), RZG2L_PIN_INFO(28, 5),
    +};
    +
     struct rzg2l_dedicated_configs {
     	const char *name;
     	u32 config;
    @@ -1512,6 +1564,36 @@ static const u32 r9a07g043_gpio_configs[] = {
     	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
     };
     
    +static const u32 r9a07g043f_gpio_configs[] = {
    +	RZG2L_GPIO_PORT_PACK(3, 0x06, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(7, 0x07, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x08, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x09, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0a, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(3, 0x0c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
    +};
    +
     static struct {
     	struct rzg2l_dedicated_configs common[35];
     	struct rzg2l_dedicated_configs rzg2l_pins[7];
    @@ -1598,6 +1680,22 @@ static struct {
     	}
     };
     
    +static struct rzg2l_dedicated_configs rzfive_dedicated_pins[10] = {
    +		{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
    +		 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
    +		{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
    +		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
    +		{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
    +		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
    +		{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
    +		{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
    +		{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
    +		{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
    +		{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
    +		{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
    +		{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
    +};
    +
     static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
     {
     	struct device_node *np = pctrl->dev->of_node;
    @@ -1880,12 +1978,12 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
     
     static struct rzg2l_pinctrl_data r9a07g043f_data = {
     	.port_pins = rzg2l_gpio_names,
    -	.port_pin_configs = r9a07g043_gpio_configs,
    -	.dedicated_pins = rzg2l_dedicated_pins.common,
    -	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
    -	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
    -	.pin_info = rzg2ul_pin_info,
    -	.ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
    +	.port_pin_configs = r9a07g043f_gpio_configs,
    +	.dedicated_pins = rzfive_dedicated_pins,
    +	.n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
    +	.n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins),
    +	.pin_info = rzfive_pin_info,
    +	.ngpioints = ARRAY_SIZE(rzfive_pin_info),
     	.irq_mask = true,
     };
     
    

  • Hello,

    Thank you for sharing the patch. But board fails to boot fully.

    Below is the boot log

    [ 0.000000] Linux version 5.10.158-cip22-g4f3d2d21ad69-dirty (navya@navya-OptiPlex-5000) (riscv64-poky-linux-gcc (GCC) 8.3.0, GNU ld (GNU Binutils) 2.31.1) #13 PREEMPT Thu Apr 13 18:28:43 IST 2023
    [ 0.000000] OF: fdt: Ignoring memory range 0x48000000 - 0x48200000
    [ 0.000000] earlycon: scif0 at MMIO 0x000000001004b800 (options '115200n8')
    [ 0.000000] printk: bootconsole [scif0] enabled
    [ 0.000000] efi: UEFI not found.
    [ 0.000000] cma: Reserved 128 MiB at 0x0000000078000000
    [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000058000000, size 128 MiB
    [ 0.000000] OF: reserved mem: initialized node linux,cma@58000000, compatible id shared-dma-pool
    [ 0.000000] Zone ranges:
    [ 0.000000] DMA32 [mem 0x0000000048200000-0x000000007fffffff]
    [ 0.000000] Normal empty
    [ 0.000000] Movable zone start for each node
    [ 0.000000] Early memory node ranges
    [ 0.000000] node 0: [mem 0x0000000048200000-0x0000000057ffffff]
    [ 0.000000] node 0: [mem 0x0000000058000000-0x000000005fffffff]
    [ 0.000000] node 0: [mem 0x0000000060000000-0x000000007fffffff]
    [ 0.000000] Initmem setup node 0 [mem 0x0000000048200000-0x000000007fffffff]
    [ 0.000000] software IO TLB: mapped [mem 0x00000000731e8000-0x00000000771e8000] (64MB)
    [ 0.000000] SBI specification v0.3 detected
    [ 0.000000] SBI implementation ID=0x1 Version=0x10000
    [ 0.000000] SBI v0.2 TIME extension detected
    [ 0.000000] SBI v0.2 IPI extension detected
    [ 0.000000] SBI v0.2 RFENCE extension detected
    [ 0.000000] riscv: ISA extensions acdfim
    [ 0.000000] riscv: ELF capabilities acdfim
    [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 225288
    [ 0.000000] Kernel command line: console=ttySC0,115200 earlycon root=/dev/mmcblk1p2 rw rootwait
    [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
    [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
    [ 0.000000] Sorting __ex_table...
    [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
    [ 0.000000] Memory: 553744K/915456K available (6145K kernel code, 4874K rwdata, 4096K rodata, 192K init, 356K bss, 230640K reserved, 131072K cma-reserved)
    [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
    [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
    [ 0.000000] rcu: RCU event tracing is enabled.
    [ 0.000000] Trampoline variant of Tasks RCU enabled.
    [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
    [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
    [ 0.000000] riscv-intc: 64 local interrupts mapped
    [ 0.000000] plic: interrupt-controller@12C00000: mapped 512 interrupts with 1 handlers for 2 contexts.
    [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
    [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x2c47f4ee7, max_idle_ns: 440795202497 ns
    [ 0.000007] sched_clock: 64 bits at 12MHz, resolution 83ns, wraps every 4398046511096ns
    [ 0.008283] Console: colour dummy device 80x25
    [ 0.012795] Calibrating delay loop (skipped), value calculated using timer frequency.. 24.00 BogoMIPS (lpj=48000)
    [ 0.023039] pid_max: default: 32768 minimum: 301
    [ 0.027806] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
    [ 0.035194] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
    [ 0.045043] rcu: Hierarchical SRCU implementation.
    [ 0.050319] Detected Renesas RZ/Five r9a07g043f
    [ 0.072115] EFI services will not be available.
    [ 0.077171] devtmpfs: initialized
    [ 0.086468] DMA: default coherent area is set
    [ 0.090930] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
    [ 0.100667] futex hash table entries: 256 (order: 0, 6144 bytes, linear)
    [ 0.112163] pinctrl core: initialized pinctrl subsystem
    [ 0.119371] NET: Registered protocol family 16
    [ 0.124178] audit: initializing netlink subsys (disabled)
    [ 0.130346] thermal_sys: Registered thermal governor 'step_wise'
    [ 0.131178] Set PMA, ID: 00, [0x00000000-0x14000000] (size: 0x14000000), SBIRET: 0x01ffffff
    [ 0.145576] audit: type=2000 audit(0.112:1): state=initialized audit_enabled=0 res=1
    [ 0.153330] Set PMA, ID: 01, [0x20000000-0x30000000] (size: 0x10000000), SBIRET: 0x09ffffff
    [ 0.161754] Set PMA, ID: 02, [0x58000000-0x60000000] (size: 0x08000000), SBIRET: 0x16ffffff
    [ 0.170093] L2CACHE: prefetch: 3
    [ 0.173304] L2CACHE: data: 3
    [ 0.176187] L2CACHE: tram: 1 0
    [ 0.179225] L2CACHE: dram_ctl:1 0
    [ 0.182539] L2CACHE: INFO
    [ 0.185145] L2CACHE: Configuration:1010100
    [ 0.189238] L2CACHE: Control:979
    [ 0.220220] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
    [ 0.227053] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
    [ 0.240085] iommu: Default domain type: Translated
    [ 0.245405] SCSI subsystem initialized
    [ 0.249726] usbcore: registered new interface driver usbfs
    [ 0.255483] usbcore: registered new interface driver hub
    [ 0.260866] usbcore: registered new device driver usb
    [ 0.266193] mc: Linux media interface: v0.10
    [ 0.270529] videodev: Linux video capture interface: v2.00
    [ 0.276050] pps_core: LinuxPPS API ver. 1 registered
    [ 0.281003] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <[email protected]>
    [ 0.290118] PTP clock support registered
    [ 0.294547] Advanced Linux Sound Architecture Driver Initialized.
    [ 0.301535] clocksource: Switched to clocksource riscv_clocksource
    [ 0.308061] VFS: Disk quotas dquot_6.6.0
    [ 0.312064] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
    [ 0.326802] NET: Registered protocol family 2
    [ 0.331462] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
    [ 0.342366] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
    [ 0.350873] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
    [ 0.358686] TCP bind hash table entries: 8192 (order: 4, 65536 bytes, linear)
    [ 0.365909] TCP: Hash tables configured (established 8192 bind 8192)
    [ 0.372423] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
    [ 0.379097] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
    [ 0.386382] NET: Registered protocol family 1
    [ 0.391402] RPC: Registered named UNIX socket transport module.
    [ 0.397382] RPC: Registered udp transport module.
    [ 0.402089] RPC: Registered tcp transport module.
    [ 0.406786] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [ 0.414400] workingset: timestamp_bits=46 max_order=18 bucket_order=0
    [ 0.429201] squashfs: version 4.0 (2009/01/31) Phillip Lougher
    [ 0.436074] NFS: Registering the id_resolver key type
    [ 0.441252] Key type id_resolver registered
    [ 0.445481] Key type id_legacy registered
    [ 0.449656] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
    [ 0.456358] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
    [ 0.463778] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
    [ 0.470783] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
    [ 0.478202] io scheduler mq-deadline registered
    [ 0.482728] io scheduler kyber registered
    [ 0.543300] SuperH (H)SCI(F) driver initialized
    [ 0.548314] 1004bc00.serial: ttySC1 at MMIO 0x1004bc00 (irq = 55, base_baud = 0) is a scif
    [ 0.557830] cacheinfo: Unable to detect cache hierarchy for CPU 0
    [ 0.573460] loop: module loaded
    [ 0.579038] tun: Universal TUN/TAP device driver, 1.6
    [ 0.584403] CAN device driver interface
    [ 0.589184] VFIO - User Level meta-driver version: 0.3
    [ 0.594382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    [ 0.600917] ehci-platform: EHCI generic platform driver
    [ 0.606801] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
    [ 0.613022] ohci-platform: OHCI generic platform driver
    [ 0.619191] usbcore: registered new interface driver usb-storage
    [ 0.625836] renesas_usbhs 11c60000.usb: host probed
    [ 0.630737] renesas_usbhs 11c60000.usb: no transceiver found
    [ 0.636559] renesas_usbhs 11c60000.usb: gadget probed
    [ 0.641696] renesas_usbhs 11c60000.usb: platform init failed.
    [ 0.647579] renesas_usbhs 11c60000.usb: probe failed (-517)
    [ 0.653861] usbcore: registered new interface driver usbtouchscreen
    [ 0.660375] i2c /dev entries driver
    [ 0.667788] ledtrig-cpu: registered to indicate activity on CPUs
    [ 0.674440] clocksource: timer@12801400: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns
    [ 0.684360] sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns
    [ 0.692269] /soc/timer@12801400: used for clocksource
    [ 0.697760] /soc/timer@12801800: used for clock events
    [ 0.703749] usbcore: registered new interface driver usbhid
    [ 0.709370] usbhid: USB HID core driver
    [ 0.716347] spi-nor spi0.0: is25wp016d (2048 Kbytes)
    [ 0.722023] 4 fixed-partitions partitions found on MTD device spi0.0
    [ 0.728456] Creating 4 MTD partitions on "spi0.0":
    [ 0.733300] 0x000000000000-0x000000020000 : "u-boot-spl"
    [ 0.746437] 0x000000020000-0x0000000e0000 : "u-boot.itb"
    [ 0.758361] 0x0000000e0000-0x000000100000 : "env"
    [ 0.770392] 0x000000100000-0x000000200000 : "test-area"
    [ 0.784685] NET: Registered protocol family 17
    [ 0.789402] can: controller area network core
    [ 0.793897] NET: Registered protocol family 29
    [ 0.798363] can: raw protocol
    [ 0.801322] can: broadcast manager protocol
    [ 0.805515] can: netlink gateway - max_hops=1
    [ 0.810144] Key type dns_resolver registered
    [ 0.814675] registered taskstats version 1
    [ 0.828939] pinctrl-rzg2l 11030000.pin-controller: gpio-ranges does not match selected SOC
    [ 0.837304] pinctrl-rzg2l 11030000.pin-controller: failed to add GPIO chip: -22
    [ 0.845083] pinctrl-rzg2l: probe of 11030000.pin-controller failed with error -22
    [ 0.856397] renesas_usbhs 11c60000.usb: host probed
    [ 0.861423] renesas_usbhs 11c60000.usb: no transceiver found
    [ 0.867283] renesas_usbhs 11c60000.usb: gadget probed
    [ 0.872393] renesas_usbhs 11c60000.usb: platform init failed.
    [ 0.878322] renesas_usbhs 11c60000.usb: probe failed (-517)
    [ 0.885838] phy_rcar_gen3_usb2 11c50200.usb-phy: deferred probe timeout, ignoring dependency
    [ 0.894543] phy_rcar_gen3_usb2 11c70200.usb-phy: deferred probe timeout, ignoring dependency
    [ 0.903246] sh-sci 1004b800.serial: deferred probe timeout, ignoring dependency
    [ 0.910720] sh-sci 1004c000.serial: deferred probe timeout, ignoring dependency
    [ 0.918182] sh-sci 1004c800.serial: deferred probe timeout, ignoring dependency
    [ 0.925676] renesas_spi 1004ac00.spi: deferred probe timeout, ignoring dependency
    [ 0.933348] rcar_canfd 10050000.can: deferred probe timeout, ignoring dependency
    [ 0.940934] ravb 11c20000.ethernet: deferred probe timeout, ignoring dependency
    [ 0.948431] ravb 11c30000.ethernet: deferred probe timeout, ignoring dependency
    [ 0.957288] renesas_usbhs 11c60000.usb: host probed
    [ 0.962247] renesas_usbhs 11c60000.usb: no transceiver found
    [ 0.968091] renesas_usbhs 11c60000.usb: gadget probed
    [ 0.973208] renesas_usbhs 11c60000.usb: platform init failed.
    [ 0.979128] renesas_usbhs 11c60000.usb: probe failed (-517)
    [ 0.985073] i2c-riic 10058000.i2c: deferred probe timeout, ignoring dependency
    [ 0.992584] i2c-riic 10058400.i2c: deferred probe timeout, ignoring dependency
    [ 1.000247] renesas_sdhi_internal_dmac 11c00000.mmc: deferred probe timeout, ignoring dependency
    [ 1.009627] renesas_mtu3 10001200.timer: deferred probe timeout, ignoring dependency
    [ 1.017627] renesas_sdhi_internal_dmac 11c10000.mmc: deferred probe timeout, ignoring dependency

  • fix_non-dedicated_rz_five_pins_attempt2.patch.txt
    diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    index bd2e7ef34b27..da28fdf8756f 100755
    --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    @@ -594,7 +594,7 @@ pinctrl: pin-controller@11030000 {
     				<0 0x110b0020 0 0x04>;
     			gpio-controller;
     			#gpio-cells = <2>;
    -			gpio-ranges = <&pinctrl 0 0 152>;
    +			gpio-ranges = <&pinctrl 0 0 216>;
     			clocks = <&cpg CPG_MOD R9A07G043F_GPIO_HCLK>;
     			power-domains = <&cpg>;
     			resets = <&cpg R9A07G043F_GPIO_RSTN>,
    diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
    index f5d8bc16c340..cf434de9a4dd 100755
    --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
    +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
    @@ -386,15 +386,12 @@ sd1_pwr_en {
     	/* Support pinctrl for MMC function of SDHI0*/
     	sdhi0_pins: sd0 {
     		sd0_data {
    -			pins =  "SD0_DATA0", "SD0_DATA1", "SD0_DATA2",
    -				"SD0_DATA3", "SD0_DATA4", "SD0_DATA5",
    -				"SD0_DATA6", "SD0_DATA7";
     			power-source  = <1800>;
     		};
     
     		sd0_ctrl {
    -			pins = "SD0_CLK", "SD0_CMD", "SD0_RST#";
     			power-source = <1800>;
    +                        pins = "SD0_CLK", "SD0_RST";
     		};
     	};
     #else
    @@ -428,25 +425,23 @@ sd0_ctrl_uhs {
     
     	sdhi1_pins: sd1 {
     		sd1_data {
    -			pins =	"SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
     			power-source  = <3300>;
     		};
     
     		sd1_ctrl {
    -			pins = "SD1_CLK", "SD1_CMD";
     			power-source  = <3300>;
    +                        pins = "SD1_CLK";
     		};
     	};
     
     	sdhi1_pins_uhs: sd1_uhs {
     		sd1_data_uhs {
    -			pins =	"SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
     			power-source  = <1800>;
     		};
     
     		sd1_ctrl_uhs {
    -			pins = "SD1_CLK", "SD1_CMD";
     			power-source  = <1800>;
    +                        pins = "SD1_CLK";
     		};
     	};
     
    diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    index 4b7d569b3464..515cb1b23b17 100644
    --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    @@ -237,6 +237,58 @@ static const int rzg2ul_pin_info[] = {
     	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
     };
     
    +static const int rzfive_pin_info[] = {
    +        RZG2L_PIN_INFO(19, 1),
    +        RZG2L_PIN_INFO(20, 0), RZG2L_PIN_INFO(20, 1), RZG2L_PIN_INFO(20, 2),
    +        RZG2L_PIN_INFO(20, 3), RZG2L_PIN_INFO(20, 4), RZG2L_PIN_INFO(20, 5),
    +        RZG2L_PIN_INFO(20, 6), RZG2L_PIN_INFO(20, 7),
    +        RZG2L_PIN_INFO(21, 1),
    +        RZG2L_PIN_INFO(22, 0), RZG2L_PIN_INFO(22, 1), RZG2L_PIN_INFO(22, 2),
    +        RZG2L_PIN_INFO(22, 3),
    +        RZG2L_PIN_INFO(23, 1), RZG2L_PIN_INFO(23, 2),
    +        RZG2L_PIN_INFO(23, 4), RZG2L_PIN_INFO(23, 5),
    +        RZG2L_PIN_INFO(24, 0), RZG2L_PIN_INFO(24, 1), RZG2L_PIN_INFO(24, 2),
    +        RZG2L_PIN_INFO(24, 3), RZG2L_PIN_INFO(24, 4), RZG2L_PIN_INFO(24, 5),
    +        RZG2L_PIN_INFO(25, 1),
    +        RZG2L_PIN_INFO(28, 0), RZG2L_PIN_INFO(28, 1), RZG2L_PIN_INFO(28, 2),
    +        RZG2L_PIN_INFO(28, 3), RZG2L_PIN_INFO(28, 4), RZG2L_PIN_INFO(28, 5),
    +	RZG2L_PIN_INFO(0,  0), RZG2L_PIN_INFO(0,  1), RZG2L_PIN_INFO(0,  2),
    +	RZG2L_PIN_INFO(0,  3),
    +	RZG2L_PIN_INFO(1,  0), RZG2L_PIN_INFO(1,  1), RZG2L_PIN_INFO(1,  2),
    +	RZG2L_PIN_INFO(1,  3), RZG2L_PIN_INFO(1,  4),
    +	RZG2L_PIN_INFO(2,  0), RZG2L_PIN_INFO(2,  1), RZG2L_PIN_INFO(2,  2),
    +	RZG2L_PIN_INFO(2,  3),
    +	RZG2L_PIN_INFO(3,  0), RZG2L_PIN_INFO(3,  1), RZG2L_PIN_INFO(3,  2),
    +	RZG2L_PIN_INFO(3,  3),
    +	RZG2L_PIN_INFO(4,  0), RZG2L_PIN_INFO(4,  1), RZG2L_PIN_INFO(4,  2),
    +	RZG2L_PIN_INFO(4,  3), RZG2L_PIN_INFO(4,  4), RZG2L_PIN_INFO(4,  5),
    +	RZG2L_PIN_INFO(5,  0), RZG2L_PIN_INFO(5,  1), RZG2L_PIN_INFO(5,  2),
    +	RZG2L_PIN_INFO(5,  3), RZG2L_PIN_INFO(5,  4),
    +	RZG2L_PIN_INFO(6,  0), RZG2L_PIN_INFO(6,  1), RZG2L_PIN_INFO(6,  2),
    +	RZG2L_PIN_INFO(6,  3), RZG2L_PIN_INFO(6,  4),
    +	RZG2L_PIN_INFO(7,  0), RZG2L_PIN_INFO(7,  1), RZG2L_PIN_INFO(7,  2),
    +	RZG2L_PIN_INFO(7,  3), RZG2L_PIN_INFO(7,  4),
    +	RZG2L_PIN_INFO(8,  0), RZG2L_PIN_INFO(8,  1), RZG2L_PIN_INFO(8,  2),
    +	RZG2L_PIN_INFO(8,  3), RZG2L_PIN_INFO(8,  4),
    +	RZG2L_PIN_INFO(9,  0), RZG2L_PIN_INFO(9,  1), RZG2L_PIN_INFO(9,  2),
    +	RZG2L_PIN_INFO(9,  3),
    +	RZG2L_PIN_INFO(10, 0), RZG2L_PIN_INFO(10, 1), RZG2L_PIN_INFO(10, 2),
    +	RZG2L_PIN_INFO(10, 3), RZG2L_PIN_INFO(10, 4),
    +	RZG2L_PIN_INFO(11, 0), RZG2L_PIN_INFO(11, 1), RZG2L_PIN_INFO(11, 2),
    +	RZG2L_PIN_INFO(11, 3),
    +	RZG2L_PIN_INFO(12, 0), RZG2L_PIN_INFO(12, 1),
    +	RZG2L_PIN_INFO(13, 0), RZG2L_PIN_INFO(13, 1), RZG2L_PIN_INFO(13, 2),
    +	RZG2L_PIN_INFO(13, 3), RZG2L_PIN_INFO(13, 4),
    +	RZG2L_PIN_INFO(14, 0), RZG2L_PIN_INFO(14, 1), RZG2L_PIN_INFO(14, 2),
    +	RZG2L_PIN_INFO(15, 0), RZG2L_PIN_INFO(15, 1), RZG2L_PIN_INFO(15, 2),
    +	RZG2L_PIN_INFO(15, 3),
    +	RZG2L_PIN_INFO(16, 0), RZG2L_PIN_INFO(16, 1),
    +	RZG2L_PIN_INFO(17, 0), RZG2L_PIN_INFO(17, 1), RZG2L_PIN_INFO(17, 2),
    +	RZG2L_PIN_INFO(17, 3),
    +	RZG2L_PIN_INFO(18, 0), RZG2L_PIN_INFO(18, 1), RZG2L_PIN_INFO(18, 2),
    +	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
    +};
    +
     struct rzg2l_dedicated_configs {
     	const char *name;
     	u32 config;
    @@ -1512,6 +1564,36 @@ static const u32 r9a07g043_gpio_configs[] = {
     	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
     };
     
    +static const u32 r9a07g043f_gpio_configs[] = {
    +	RZG2L_GPIO_PORT_PACK(3, 0x06, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(8, 0x07, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x08, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x09, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0a, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x0c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
    +};
    +
     static struct {
     	struct rzg2l_dedicated_configs common[35];
     	struct rzg2l_dedicated_configs rzg2l_pins[7];
    @@ -1598,6 +1680,38 @@ static struct {
     	}
     };
     
    +//static struct rzg2l_dedicated_configs rzfive_dedicated_pins[15] = {
    +static struct {
    +        struct rzg2l_dedicated_configs common[15];
    +//        struct rzfive_dedicated_configs rzg2l_pins[7];
    +} rzfive_dedicated_pins = {
    +        .common = {
    +		{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
    +		 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
    +		{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
    +		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
    +		{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
    +		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
    +                { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
    +                { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
    +                { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
    +                { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
    +                { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
    +                { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
    +                { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
    +		{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
    +		{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
    +		{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
    +		{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
    +		{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
    +	}
    +};
    +
     static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
     {
     	struct device_node *np = pctrl->dev->of_node;
    @@ -1612,6 +1726,11 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
     		dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
     		return ret;
     	}
    +	dev_info(pctrl->dev,"test");
    +	dev_info(pctrl->dev,"args0: %i",of_args.args[0]);
    +	dev_info(pctrl->dev,"args1: %i",of_args.args[1]);
    +	dev_info(pctrl->dev,"args2: %i",of_args.args[2]);
    +	dev_info(pctrl->dev,"nportpins: %i",pctrl->data->n_port_pins);
     
     	if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
     	    of_args.args[2] != pctrl->data->n_port_pins) {
    @@ -1877,18 +1996,30 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
     	.ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
     	.irq_mask = false,
     };
    -
    +/*
     static struct rzg2l_pinctrl_data r9a07g043f_data = {
     	.port_pins = rzg2l_gpio_names,
    -	.port_pin_configs = r9a07g043_gpio_configs,
    -	.dedicated_pins = rzg2l_dedicated_pins.common,
    -	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
    -	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
    -	.pin_info = rzg2ul_pin_info,
    -	.ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
    +	.port_pin_configs = r9a07g043f_gpio_configs,
    +	.dedicated_pins = rzfive_dedicated_pins,
    +	.n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
    +	.n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins),
    +	.pin_info = rzfive_pin_info,
    +	.ngpioints = ARRAY_SIZE(rzfive_pin_info),
     	.irq_mask = true,
    +};*/
    +
    +static struct rzg2l_pinctrl_data r9a07g043f_data = {
    +        .port_pins = rzg2l_gpio_names,
    +        .port_pin_configs = r9a07g043f_gpio_configs,
    +        .dedicated_pins = rzfive_dedicated_pins.common,
    +        .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
    +        .n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins.common),
    +        .pin_info = rzfive_pin_info,
    +        .ngpioints = ARRAY_SIZE(rzfive_pin_info),
    +        .irq_mask = true,
     };
     
    +
     static struct rzg2l_pinctrl_data r9a07g044_data = {
     	.port_pins = rzg2l_gpio_names,
     	.port_pin_configs = rzg2l_gpio_configs,
    

    Still not complete but worth to try.

  • This should be ok, at least with EVK.

    fix_non-dedicated_rz_five_pins_attempt3.patch.txt
    diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    index bd2e7ef34b27..da28fdf8756f 100755
    --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    @@ -594,7 +594,7 @@ pinctrl: pin-controller@11030000 {
     				<0 0x110b0020 0 0x04>;
     			gpio-controller;
     			#gpio-cells = <2>;
    -			gpio-ranges = <&pinctrl 0 0 152>;
    +			gpio-ranges = <&pinctrl 0 0 216>;
     			clocks = <&cpg CPG_MOD R9A07G043F_GPIO_HCLK>;
     			power-domains = <&cpg>;
     			resets = <&cpg R9A07G043F_GPIO_RSTN>,
    diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
    index f5d8bc16c340..9c845a72014a 100755
    --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
    +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
    @@ -104,8 +104,7 @@ vccq_sdhi0: regulator-vccq-sdhi0 {
     		gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
     
     		gpios-states = <1>;
    -		states = <3300000 1
    -			  1800000 0>;
    +		states = <3300000 1>, <1800000 0>;
     	};
     #endif
     
    @@ -119,8 +118,7 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
     		gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>;
     
     		gpios-states = <1>;
    -		states = <3300000 1
    -			  1800000 0>;
    +		states = <3300000 1>, <1800000 0>;
     	};
     
     	x1_clk: x1-clock {
    @@ -386,41 +384,44 @@ sd1_pwr_en {
     	/* Support pinctrl for MMC function of SDHI0*/
     	sdhi0_pins: sd0 {
     		sd0_data {
    -			pins =  "SD0_DATA0", "SD0_DATA1", "SD0_DATA2",
    -				"SD0_DATA3", "SD0_DATA4", "SD0_DATA5",
    -				"SD0_DATA6", "SD0_DATA7";
     			power-source  = <1800>;
     		};
     
     		sd0_ctrl {
    -			pins = "SD0_CLK", "SD0_CMD", "SD0_RST#";
     			power-source = <1800>;
    +                        pins = "SD0_CLK", "SD0_RST#";
     		};
     	};
    +        sdhi0_pins_uhs: sd0_uhs {
    +                sd0_data_uhs {
    +                        power-source  = <1800>;
    +                };
    +
    +                sd0_ctrl_uhs {
    +                        pins = "SD0_CLK", "SD0_RST#";
    +                        power-source  = <1800>;
    +                };
    +        };
     #else
     	/* Support pinctrl for SD function of SDHI0 */
     	sdhi0_pins: sd0 {
     		sd0_data {
    -			pins =  "SD0_DATA0", "SD0_DATA1", "SD0_DATA2",
    -				"SD0_DATA3";
     			power-source  = <3300>;
     		};
     
     		sd0_ctrl {
    -			pins = "SD0_CLK", "SD0_CMD";
    +			pins = "SD0_CLK", "SD0_RST#";
     			power-source = <3300>;
     		};
     	};
     
     	sdhi0_pins_uhs: sd0_uhs {
     		sd0_data_uhs {
    -			pins =	"SD0_DATA0", "SD0_DATA1", "SD0_DATA2",
    -				"SD0_DATA3";
     			power-source  = <1800>;
     		};
     
     		sd0_ctrl_uhs {
    -			pins = "SD0_CLK", "SD0_CMD";
    +			pins = "SD0_CLK, "SD_RST#";
     			power-source  = <1800>;
     		};
     	};
    @@ -428,26 +429,26 @@ sd0_ctrl_uhs {
     
     	sdhi1_pins: sd1 {
     		sd1_data {
    -			pins =	"SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
     			power-source  = <3300>;
     		};
     
     		sd1_ctrl {
    -			pins = "SD1_CLK", "SD1_CMD";
     			power-source  = <3300>;
    +                        pins = "SD1_CLK";
     		};
    +
     	};
     
     	sdhi1_pins_uhs: sd1_uhs {
     		sd1_data_uhs {
    -			pins =	"SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
     			power-source  = <1800>;
     		};
     
     		sd1_ctrl_uhs {
    -			pins = "SD1_CLK", "SD1_CMD";
     			power-source  = <1800>;
    +                        pins = "SD1_CLK";
     		};
    +
     	};
     
     	sound_clk_pins: sound_clk {
    @@ -502,6 +503,7 @@ &sdhi0 {
     	pinctrl-0 = <&sdhi0_pins>;
     	pinctrl-1 = <&sdhi0_pins>;
     	pinctrl-names = "default", "state_uhs";
    +	cd-gpios = <&pinctrl RZG2L_GPIO(0, 0) GPIO_ACTIVE_LOW>;
     
     	vmmc-supply = <&reg_3p3v>;
     	vqmmc-supply = <&reg_1p8v>;
    diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    index 4b7d569b3464..515cb1b23b17 100644
    --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    @@ -237,6 +237,58 @@ static const int rzg2ul_pin_info[] = {
     	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
     };
     
    +static const int rzfive_pin_info[] = {
    +        RZG2L_PIN_INFO(19, 1),
    +        RZG2L_PIN_INFO(20, 0), RZG2L_PIN_INFO(20, 1), RZG2L_PIN_INFO(20, 2),
    +        RZG2L_PIN_INFO(20, 3), RZG2L_PIN_INFO(20, 4), RZG2L_PIN_INFO(20, 5),
    +        RZG2L_PIN_INFO(20, 6), RZG2L_PIN_INFO(20, 7),
    +        RZG2L_PIN_INFO(21, 1),
    +        RZG2L_PIN_INFO(22, 0), RZG2L_PIN_INFO(22, 1), RZG2L_PIN_INFO(22, 2),
    +        RZG2L_PIN_INFO(22, 3),
    +        RZG2L_PIN_INFO(23, 1), RZG2L_PIN_INFO(23, 2),
    +        RZG2L_PIN_INFO(23, 4), RZG2L_PIN_INFO(23, 5),
    +        RZG2L_PIN_INFO(24, 0), RZG2L_PIN_INFO(24, 1), RZG2L_PIN_INFO(24, 2),
    +        RZG2L_PIN_INFO(24, 3), RZG2L_PIN_INFO(24, 4), RZG2L_PIN_INFO(24, 5),
    +        RZG2L_PIN_INFO(25, 1),
    +        RZG2L_PIN_INFO(28, 0), RZG2L_PIN_INFO(28, 1), RZG2L_PIN_INFO(28, 2),
    +        RZG2L_PIN_INFO(28, 3), RZG2L_PIN_INFO(28, 4), RZG2L_PIN_INFO(28, 5),
    +	RZG2L_PIN_INFO(0,  0), RZG2L_PIN_INFO(0,  1), RZG2L_PIN_INFO(0,  2),
    +	RZG2L_PIN_INFO(0,  3),
    +	RZG2L_PIN_INFO(1,  0), RZG2L_PIN_INFO(1,  1), RZG2L_PIN_INFO(1,  2),
    +	RZG2L_PIN_INFO(1,  3), RZG2L_PIN_INFO(1,  4),
    +	RZG2L_PIN_INFO(2,  0), RZG2L_PIN_INFO(2,  1), RZG2L_PIN_INFO(2,  2),
    +	RZG2L_PIN_INFO(2,  3),
    +	RZG2L_PIN_INFO(3,  0), RZG2L_PIN_INFO(3,  1), RZG2L_PIN_INFO(3,  2),
    +	RZG2L_PIN_INFO(3,  3),
    +	RZG2L_PIN_INFO(4,  0), RZG2L_PIN_INFO(4,  1), RZG2L_PIN_INFO(4,  2),
    +	RZG2L_PIN_INFO(4,  3), RZG2L_PIN_INFO(4,  4), RZG2L_PIN_INFO(4,  5),
    +	RZG2L_PIN_INFO(5,  0), RZG2L_PIN_INFO(5,  1), RZG2L_PIN_INFO(5,  2),
    +	RZG2L_PIN_INFO(5,  3), RZG2L_PIN_INFO(5,  4),
    +	RZG2L_PIN_INFO(6,  0), RZG2L_PIN_INFO(6,  1), RZG2L_PIN_INFO(6,  2),
    +	RZG2L_PIN_INFO(6,  3), RZG2L_PIN_INFO(6,  4),
    +	RZG2L_PIN_INFO(7,  0), RZG2L_PIN_INFO(7,  1), RZG2L_PIN_INFO(7,  2),
    +	RZG2L_PIN_INFO(7,  3), RZG2L_PIN_INFO(7,  4),
    +	RZG2L_PIN_INFO(8,  0), RZG2L_PIN_INFO(8,  1), RZG2L_PIN_INFO(8,  2),
    +	RZG2L_PIN_INFO(8,  3), RZG2L_PIN_INFO(8,  4),
    +	RZG2L_PIN_INFO(9,  0), RZG2L_PIN_INFO(9,  1), RZG2L_PIN_INFO(9,  2),
    +	RZG2L_PIN_INFO(9,  3),
    +	RZG2L_PIN_INFO(10, 0), RZG2L_PIN_INFO(10, 1), RZG2L_PIN_INFO(10, 2),
    +	RZG2L_PIN_INFO(10, 3), RZG2L_PIN_INFO(10, 4),
    +	RZG2L_PIN_INFO(11, 0), RZG2L_PIN_INFO(11, 1), RZG2L_PIN_INFO(11, 2),
    +	RZG2L_PIN_INFO(11, 3),
    +	RZG2L_PIN_INFO(12, 0), RZG2L_PIN_INFO(12, 1),
    +	RZG2L_PIN_INFO(13, 0), RZG2L_PIN_INFO(13, 1), RZG2L_PIN_INFO(13, 2),
    +	RZG2L_PIN_INFO(13, 3), RZG2L_PIN_INFO(13, 4),
    +	RZG2L_PIN_INFO(14, 0), RZG2L_PIN_INFO(14, 1), RZG2L_PIN_INFO(14, 2),
    +	RZG2L_PIN_INFO(15, 0), RZG2L_PIN_INFO(15, 1), RZG2L_PIN_INFO(15, 2),
    +	RZG2L_PIN_INFO(15, 3),
    +	RZG2L_PIN_INFO(16, 0), RZG2L_PIN_INFO(16, 1),
    +	RZG2L_PIN_INFO(17, 0), RZG2L_PIN_INFO(17, 1), RZG2L_PIN_INFO(17, 2),
    +	RZG2L_PIN_INFO(17, 3),
    +	RZG2L_PIN_INFO(18, 0), RZG2L_PIN_INFO(18, 1), RZG2L_PIN_INFO(18, 2),
    +	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
    +};
    +
     struct rzg2l_dedicated_configs {
     	const char *name;
     	u32 config;
    @@ -1512,6 +1564,36 @@ static const u32 r9a07g043_gpio_configs[] = {
     	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
     };
     
    +static const u32 r9a07g043f_gpio_configs[] = {
    +	RZG2L_GPIO_PORT_PACK(3, 0x06, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(8, 0x07, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x08, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x09, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0a, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x0c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
    +};
    +
     static struct {
     	struct rzg2l_dedicated_configs common[35];
     	struct rzg2l_dedicated_configs rzg2l_pins[7];
    @@ -1598,6 +1680,38 @@ static struct {
     	}
     };
     
    +//static struct rzg2l_dedicated_configs rzfive_dedicated_pins[15] = {
    +static struct {
    +        struct rzg2l_dedicated_configs common[15];
    +//        struct rzfive_dedicated_configs rzg2l_pins[7];
    +} rzfive_dedicated_pins = {
    +        .common = {
    +		{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0,
    +		 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) },
    +		{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
    +		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
    +		{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
    +		 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
    +                { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
    +                { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
    +                { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
    +                { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
    +                { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
    +                { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
    +                { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
    +                 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
    +		{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
    +		{ "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
    +		{ "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
    +		{ "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
    +		{ "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
    +	}
    +};
    +
     static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
     {
     	struct device_node *np = pctrl->dev->of_node;
    @@ -1612,6 +1726,11 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
     		dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
     		return ret;
     	}
    +	dev_info(pctrl->dev,"test");
    +	dev_info(pctrl->dev,"args0: %i",of_args.args[0]);
    +	dev_info(pctrl->dev,"args1: %i",of_args.args[1]);
    +	dev_info(pctrl->dev,"args2: %i",of_args.args[2]);
    +	dev_info(pctrl->dev,"nportpins: %i",pctrl->data->n_port_pins);
     
     	if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
     	    of_args.args[2] != pctrl->data->n_port_pins) {
    @@ -1877,18 +1996,30 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
     	.ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
     	.irq_mask = false,
     };
    -
    +/*
     static struct rzg2l_pinctrl_data r9a07g043f_data = {
     	.port_pins = rzg2l_gpio_names,
    -	.port_pin_configs = r9a07g043_gpio_configs,
    -	.dedicated_pins = rzg2l_dedicated_pins.common,
    -	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
    -	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
    -	.pin_info = rzg2ul_pin_info,
    -	.ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
    +	.port_pin_configs = r9a07g043f_gpio_configs,
    +	.dedicated_pins = rzfive_dedicated_pins,
    +	.n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
    +	.n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins),
    +	.pin_info = rzfive_pin_info,
    +	.ngpioints = ARRAY_SIZE(rzfive_pin_info),
     	.irq_mask = true,
    +};*/
    +
    +static struct rzg2l_pinctrl_data r9a07g043f_data = {
    +        .port_pins = rzg2l_gpio_names,
    +        .port_pin_configs = r9a07g043f_gpio_configs,
    +        .dedicated_pins = rzfive_dedicated_pins.common,
    +        .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
    +        .n_dedicated_pins = ARRAY_SIZE(rzfive_dedicated_pins.common),
    +        .pin_info = rzfive_pin_info,
    +        .ngpioints = ARRAY_SIZE(rzfive_pin_info),
    +        .irq_mask = true,
     };
     
    +
     static struct rzg2l_pinctrl_data r9a07g044_data = {
     	.port_pins = rzg2l_gpio_names,
     	.port_pin_configs = rzg2l_gpio_configs,
    

  • Hello,

    Thank you for sharing the patch. With patch we are able to configure the pins without errors.
    But, when we configured these P24 bank pins as interfaces it is not working.
    Hence we tried it as a GPIO and tried to toggle in EVK board, but it is failing.
    Always the voltage is showing as 1v4 in EVK board.
    Is there any additional changes required?

    Regards.

  • Ok forget that patch, try this instead.

    0001-Supports-function-allocation-for-ports-19-to-28.patch.txt
    From b63d8fae7b94998e83dbdaa928e50b2a9a6a33f8 Mon Sep 17 00:00:00 2001
    From: Shinji Hirai <[email protected]>
    Date: Tue, 7 Mar 2023 13:46:49 +0900
    Subject: [PATCH] Supports function allocation for ports 19 to 28
    
    ---
     arch/riscv/boot/dts/renesas/r9a07g043f.dtsi |   2 +-
     drivers/pinctrl/renesas/pinctrl-rzg2l.c     | 175 +++++++++++++++++---
     2 files changed, 152 insertions(+), 25 deletions(-)
     mode change 100755 => 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    
    diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    old mode 100755
    new mode 100644
    index bd2e7ef34b27..4e6a73e2f399
    --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
    @@ -594,7 +594,7 @@ pinctrl: pin-controller@11030000 {
     				<0 0x110b0020 0 0x04>;
     			gpio-controller;
     			#gpio-cells = <2>;
    -			gpio-ranges = <&pinctrl 0 0 152>;
    +			gpio-ranges = <&pinctrl 0 0 232>;
     			clocks = <&cpg CPG_MOD R9A07G043F_GPIO_HCLK>;
     			power-domains = <&cpg>;
     			resets = <&cpg R9A07G043F_GPIO_RSTN>,
    diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    index 4b7d569b3464..fb4ef1e0a68b 100644
    --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
    @@ -18,6 +18,7 @@
     #include <linux/pinctrl/pinctrl.h>
     #include <linux/pinctrl/pinmux.h>
     #include <linux/spinlock.h>
    +#include <linux/sys_soc.h>
     
     #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
     
    @@ -99,6 +100,13 @@
     #define QSPI			(0x3008)
     #define ETH_CH(n)		(0x300C + (n) * 4)
     
    +#define P_EX(n)			(0x0000 + 0x06 + (n-19))
    +#define PM_EX(n)		(0x0100 + 0x0c + (n-19) * 2)
    +#define PMC_EX(n)		(0x0200 + 0x06 + (n-19))
    +#define PFC_EX(n)		(0x0400 + 0x18 + (n-19) * 4)
    +#define PIN_EX(n)		(0x0800 + 0x06 + (n-19))
    +#define ISEL_EX(n)		(0x2C00 + 0x30 + (n-19) * 8)
    +
     #define PVDD_1800		1	/* I/O domain voltage <= 1.8V */
     #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
     #define ETH_PVDD_2500		BIT(1)	/* Ether I/O voltage 2.5V */
    @@ -237,6 +245,60 @@ static const int rzg2ul_pin_info[] = {
     	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
     };
     
    +static const int rzfive_pin_info[] = {
    +	RZG2L_PIN_INFO(0,  0), RZG2L_PIN_INFO(0,  1), RZG2L_PIN_INFO(0,  2),
    +	RZG2L_PIN_INFO(0,  3),
    +	RZG2L_PIN_INFO(1,  0), RZG2L_PIN_INFO(1,  1), RZG2L_PIN_INFO(1,  2),
    +	RZG2L_PIN_INFO(1,  3), RZG2L_PIN_INFO(1,  4),
    +	RZG2L_PIN_INFO(2,  0), RZG2L_PIN_INFO(2,  1), RZG2L_PIN_INFO(2,  2),
    +	RZG2L_PIN_INFO(2,  3),
    +	RZG2L_PIN_INFO(3,  0), RZG2L_PIN_INFO(3,  1), RZG2L_PIN_INFO(3,  2),
    +	RZG2L_PIN_INFO(3,  3),
    +	RZG2L_PIN_INFO(4,  0), RZG2L_PIN_INFO(4,  1), RZG2L_PIN_INFO(4,  2),
    +	RZG2L_PIN_INFO(4,  3), RZG2L_PIN_INFO(4,  4), RZG2L_PIN_INFO(4,  5),
    +	RZG2L_PIN_INFO(5,  0), RZG2L_PIN_INFO(5,  1), RZG2L_PIN_INFO(5,  2),
    +	RZG2L_PIN_INFO(5,  3), RZG2L_PIN_INFO(5,  4),
    +	RZG2L_PIN_INFO(6,  0), RZG2L_PIN_INFO(6,  1), RZG2L_PIN_INFO(6,  2),
    +	RZG2L_PIN_INFO(6,  3), RZG2L_PIN_INFO(6,  4),
    +	RZG2L_PIN_INFO(7,  0), RZG2L_PIN_INFO(7,  1), RZG2L_PIN_INFO(7,  2),
    +	RZG2L_PIN_INFO(7,  3), RZG2L_PIN_INFO(7,  4),
    +	RZG2L_PIN_INFO(8,  0), RZG2L_PIN_INFO(8,  1), RZG2L_PIN_INFO(8,  2),
    +	RZG2L_PIN_INFO(8,  3), RZG2L_PIN_INFO(8,  4),
    +	RZG2L_PIN_INFO(9,  0), RZG2L_PIN_INFO(9,  1), RZG2L_PIN_INFO(9,  2),
    +	RZG2L_PIN_INFO(9,  3),
    +	RZG2L_PIN_INFO(10, 0), RZG2L_PIN_INFO(10, 1), RZG2L_PIN_INFO(10, 2),
    +	RZG2L_PIN_INFO(10, 3), RZG2L_PIN_INFO(10, 4),
    +	RZG2L_PIN_INFO(11, 0), RZG2L_PIN_INFO(11, 1), RZG2L_PIN_INFO(11, 2),
    +	RZG2L_PIN_INFO(11, 3),
    +	RZG2L_PIN_INFO(12, 0), RZG2L_PIN_INFO(12, 1),
    +	RZG2L_PIN_INFO(13, 0), RZG2L_PIN_INFO(13, 1), RZG2L_PIN_INFO(13, 2),
    +	RZG2L_PIN_INFO(13, 3), RZG2L_PIN_INFO(13, 4),
    +	RZG2L_PIN_INFO(14, 0), RZG2L_PIN_INFO(14, 1), RZG2L_PIN_INFO(14, 2),
    +	RZG2L_PIN_INFO(15, 0), RZG2L_PIN_INFO(15, 1), RZG2L_PIN_INFO(15, 2),
    +	RZG2L_PIN_INFO(15, 3),
    +	RZG2L_PIN_INFO(16, 0), RZG2L_PIN_INFO(16, 1),
    +	RZG2L_PIN_INFO(17, 0), RZG2L_PIN_INFO(17, 1), RZG2L_PIN_INFO(17, 2),
    +	RZG2L_PIN_INFO(17, 3),
    +	RZG2L_PIN_INFO(18, 0), RZG2L_PIN_INFO(18, 1), RZG2L_PIN_INFO(18, 2),
    +	RZG2L_PIN_INFO(18, 3), RZG2L_PIN_INFO(18, 4), RZG2L_PIN_INFO(18, 5),
    +	RZG2L_PIN_INFO(19, 0), RZG2L_PIN_INFO(19, 1), RZG2L_PIN_INFO(19, 2),
    +	RZG2L_PIN_INFO(20, 0), RZG2L_PIN_INFO(20, 1), RZG2L_PIN_INFO(20, 2),
    +	RZG2L_PIN_INFO(20, 3), RZG2L_PIN_INFO(20, 4), RZG2L_PIN_INFO(20, 5),
    +	RZG2L_PIN_INFO(20, 6), RZG2L_PIN_INFO(20, 7),
    +	RZG2L_PIN_INFO(21, 0), RZG2L_PIN_INFO(21, 1),
    +	RZG2L_PIN_INFO(22, 0), RZG2L_PIN_INFO(22, 1), RZG2L_PIN_INFO(22, 2),
    +	RZG2L_PIN_INFO(22, 3),
    +	RZG2L_PIN_INFO(23, 0), RZG2L_PIN_INFO(23, 1), RZG2L_PIN_INFO(23, 2),
    +	RZG2L_PIN_INFO(23, 3), RZG2L_PIN_INFO(23, 4), RZG2L_PIN_INFO(23, 5),
    +	RZG2L_PIN_INFO(24, 0), RZG2L_PIN_INFO(24, 1), RZG2L_PIN_INFO(24, 2),
    +	RZG2L_PIN_INFO(24, 3), RZG2L_PIN_INFO(24, 4), RZG2L_PIN_INFO(24, 5),
    +	RZG2L_PIN_INFO(25, 0), RZG2L_PIN_INFO(25, 1),
    +	RZG2L_PIN_INFO(26, 0), // dummy
    +	RZG2L_PIN_INFO(27, 0), // dummy
    +	RZG2L_PIN_INFO(28, 0), RZG2L_PIN_INFO(28, 1), RZG2L_PIN_INFO(28, 2),
    +	RZG2L_PIN_INFO(28, 3), RZG2L_PIN_INFO(28, 4), RZG2L_PIN_INFO(28, 5),
    +};
    +
     struct rzg2l_dedicated_configs {
     	const char *name;
     	u32 config;
    @@ -284,6 +346,11 @@ struct rzg2l_pinctrl {
     static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
     static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
     
    +static const struct soc_device_attribute rzfive_match[] = {
    +	{ .family = "RZ/Five" },
    +	{ /* sentinel*/ }
    +};
    +
     static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
     				       u8 port, u8 pin, u8 func)
     {
    @@ -292,31 +359,59 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
     
     	spin_lock_irqsave(&pctrl->lock, flags);
     
    -	/* Set pin to 'Non-use (Hi-Z input protection)'  */
    -	reg = readw(pctrl->base + PM(port));
    -	reg &= ~(PM_MASK << (pin * 2));
    -	writew(reg, pctrl->base + PM(port));
    +	if (soc_device_match(rzfive_match) && (port > 18)) {
    +		/* Set pin to 'Non-use (Hi-Z input protection)'  */
    +		reg = readw(pctrl->base + PM_EX(port));
    +		reg &= ~(PM_MASK << (pin * 2));
    +		writew(reg, pctrl->base + PM_EX(port));
     
    -	/* Temporarily switch to GPIO mode with PMC register */
    -	reg = readb(pctrl->base + PMC(port));
    -	writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
    +		/* Temporarily switch to GPIO mode with PMC register */
    +		reg = readb(pctrl->base + PMC_EX(port));
    +		writeb(reg & ~BIT(pin), pctrl->base + PMC_EX(port));
     
    -	/* Set the PWPR register to allow PFC register to write */
    -	writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */
    -	writel(PWPR_PFCWE, pctrl->base + PWPR);  /* B0WI=0, PFCWE=1 */
    +		/* Set the PWPR register to allow PFC register to write */
    +		writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */
    +		writel(PWPR_PFCWE, pctrl->base + PWPR);  /* B0WI=0, PFCWE=1 */
     
    -	/* Select Pin function mode with PFC register */
    -	reg = readl(pctrl->base + PFC(port));
    -	reg &= ~(PFC_MASK << (pin * 4));
    -	writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
    +		/* Select Pin function mode with PFC register */
    +		reg = readl(pctrl->base + PFC_EX(port));
    +		reg &= ~(PFC_MASK << (pin * 4));
    +		writel(reg | (func << (pin * 4)), pctrl->base + PFC_EX(port));
     
    -	/* Set the PWPR register to be write-protected */
    -	writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */
    -	writel(PWPR_B0WI, pctrl->base + PWPR);  /* B0WI=1, PFCWE=0 */
    +		/* Set the PWPR register to be write-protected */
    +		writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */
    +		writel(PWPR_B0WI, pctrl->base + PWPR);  /* B0WI=1, PFCWE=0 */
     
    -	/* Switch to Peripheral pin function with PMC register */
    -	reg = readb(pctrl->base + PMC(port));
    -	writeb(reg | BIT(pin), pctrl->base + PMC(port));
    +		/* Switch to Peripheral pin function with PMC register */
    +		reg = readb(pctrl->base + PMC_EX(port));
    +		writeb(reg | BIT(pin), pctrl->base + PMC_EX(port));
    +	} else {
    +		/* Set pin to 'Non-use (Hi-Z input protection)'  */
    +		reg = readw(pctrl->base + PM(port));
    +		reg &= ~(PM_MASK << (pin * 2));
    +		writew(reg, pctrl->base + PM(port));
    +
    +		/* Temporarily switch to GPIO mode with PMC register */
    +		reg = readb(pctrl->base + PMC(port));
    +		writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
    +
    +		/* Set the PWPR register to allow PFC register to write */
    +		writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */
    +		writel(PWPR_PFCWE, pctrl->base + PWPR);  /* B0WI=0, PFCWE=1 */
    +
    +		/* Select Pin function mode with PFC register */
    +		reg = readl(pctrl->base + PFC(port));
    +		reg &= ~(PFC_MASK << (pin * 4));
    +		writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
    +
    +		/* Set the PWPR register to be write-protected */
    +		writel(0x0, pctrl->base + PWPR);        /* B0WI=0, PFCWE=0 */
    +		writel(PWPR_B0WI, pctrl->base + PWPR);  /* B0WI=1, PFCWE=0 */
    +
    +		/* Switch to Peripheral pin function with PMC register */
    +		reg = readb(pctrl->base + PMC(port));
    +		writeb(reg | BIT(pin), pctrl->base + PMC(port));
    +	}
     
     	spin_unlock_irqrestore(&pctrl->lock, flags);
     };
    @@ -1512,6 +1607,38 @@ static const u32 r9a07g043_gpio_configs[] = {
     	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
     };
     
    +static const u32 r9a07g043f_gpio_configs[] = {
    +	RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(3, 0x06, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(8, 0x07, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x08, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(4, 0x09, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0a, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(6, 0x0b, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(2, 0x0c, RZG2L_MPXED_PIN_FUNCS),
    +	RZG2L_GPIO_PORT_PACK(1, 0x0d, RZG2L_MPXED_PIN_FUNCS),	//dummy
    +	RZG2L_GPIO_PORT_PACK(1, 0x0e, RZG2L_MPXED_PIN_FUNCS),	//dummy
    +	RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS),
    +};
    +
     static struct {
     	struct rzg2l_dedicated_configs common[35];
     	struct rzg2l_dedicated_configs rzg2l_pins[7];
    @@ -1880,12 +2007,12 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
     
     static struct rzg2l_pinctrl_data r9a07g043f_data = {
     	.port_pins = rzg2l_gpio_names,
    -	.port_pin_configs = r9a07g043_gpio_configs,
    +	.port_pin_configs = r9a07g043f_gpio_configs,
     	.dedicated_pins = rzg2l_dedicated_pins.common,
    -	.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
    +	.n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
     	.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
    -	.pin_info = rzg2ul_pin_info,
    -	.ngpioints = ARRAY_SIZE(rzg2ul_pin_info),
    +	.pin_info = rzfive_pin_info,
    +	.ngpioints = ARRAY_SIZE(rzfive_pin_info),
     	.irq_mask = true,
     };
     
    -- 
    2.25.1
    
    

  • Hello,

    With the latest shared patch also, as interface or as GPIO, P24 bank pins are not working.

    Regards.

  • Hello, 

    Is there any update on this case?

    Regards

  • Hello,

    Is there any update on this issue? 

    Regards.

  • Hello

    We are waiting for the updated VLP release for RZ-V.

    Can you please provide any information on when will be the next major VLP release for RZ-V?

    Regards.

  • Hello

    We are waiting for the updated VLP release for RZ-V.

    Can you please provide any information on when will be the next major VLP release for RZ-V?

    Regards.

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