build scripts error

Did you download mbedtls and put it in the same directory as rzg_trusted-firmware-a ?

https://github.com/renesas-rz/rzg2_bsp_scripts/blob/master/build_scripts/Repository%20Installs.txt

---------------------------------------------------
mbed
---------------------------------------------------
NOTES: mbed code is needed to build Trusted Firmware-A in BSP v1.0.5+

Clone repository and check out branch:
$ git clone github.com/.../mbedtls.git
$ cd mbedtls
$ git checkout mbedtls-2.16.3
$ cd ..

├── build_scripts
│   ├── mbedtls/                   <<<<<< download
│   ├── renesas-u-boot-cip/        <<<<<< download
│   ├── rzg2_flash_writer/         <<<<<< download
│   ├── rzg_trusted-firmware-a/    <<<<<< download
│   ├── rz_linux-cip/              <<<<<< download
│   ├── build.sh
│   ├── build_xxxx.sh
│   ├── build_xxxx.sh
│   ├── README.html
│   └── README.md

Hi Chris,

I managed to add all the missing files in mbedtls and successfully build the aft.

And now its able to boot BL2 also with out RAM issue.

But When I entered Uboot the processor is stuck at DRAM: line

here is the log:

>INFO:    ARM GICv2 driver initialized
NOTICE:  BL2: RZ/G2 Initial Program Loader(CA57) Rev.3.0.3
NOTICE:  BL2: PRR is RZ/G2N Ver.1.1
NOTICE:  BL2: Board is HiHope RZ/G2N Rev.2.0
NOTICE:  BL2: Boot device is eMMC(50MHz x8)
NOTICE:  BL2: DDR3200(rev.0.41)
NOTICE:  BL2: [COLD_BOOT]
NOTICE:  BL2: DRAM Split is OFF
NOTICE:  BL2: QoS is default setting(rev.0.09)
NOTICE:  BL2: DRAM refresh interval 1.95 usec
NOTICE:  BL2: Periodic Write DQ Training
NOTICE:  BL2: DRAM don't have ECC configuration
NOTICE:  BL2: CH0: 400000000 - 4ffffffff, 4 GiB
NOTICE:  BL2: Lossy Decomp areas
NOTICE:       Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
NOTICE:       Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
NOTICE:       Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
NOTICE:  BL2: FDT at 0xe631fa70
NOTICE:  BL2: v2.7(release):v2.5/rzg2l-1.00-2008-gac8a2c2f2-dirty
NOTICE:  BL2: Built : 16:59:56, Jan  4 2024
NOTICE:  BL2: Normal boot
INFO:    BL2: Doing platform setup
INFO:    BL2: Loading image id 3
NOTICE:  BL2: eMMC boot from partition 1
NOTICE:  BL2: Load dst=0xe631f300 src=(p:1)0x30000(384) len=0x200(1)
NOTICE:  BL2: Load dst=0x43f00000 src=(p:1)0x30400(386) len=0x1800(12)
WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
INFO:    Loading image id=3 at address 0x44000000
NOTICE:  rcar_file_len: len: 0x0003e000
NOTICE:  BL2: Load dst=0x44000000 src=(p:1)0x40000(512) len=0x3e000(496)
INFO:    Image id=3 loaded: 0x44000000 - 0x4403e000
INFO:    BL2: Loading image id 5
INFO:    Loading image id=5 at address 0x50000000
NOTICE:  rcar_file_len: len: 0x00100000
NOTICE:  BL2: Load dst=0x50000000 src=(p:2)0x0(0) len=0x100000(2048)
INFO:    Image id=5 loaded: 0x50000000 - 0x50100000
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0x44000000
INFO:    SPSR = 0x3cd
VERBOSE: Argument #0 = 0xe631f560
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0


U-Boot 2021.10 (Sep 20 2023 - 02:21:30 +0000)

CPU:   Renesas Electronics R8A774B1 rev 1.1
Model: HopeRun HiHope RZ/G2N with sub board
DRAM:

I Think the Uboot is now copied from EMMC to DDR and started execution (correct me if I am wrong)..

And its stuck in the same DDR.

Whether I have change the RAM configuration in uboot also, If so which file I can change it?

Using Build Script I could able to build Uboot also, at first an error poped up:

PATH=/opt/linaro/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu/bin:/opt/linaro/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin ; export CROSS_COMPILE=aarch64-linux-gnu-
cd renesas-u-boot-cip

ERROR: Default configuration file configs/r8a774b1_hihope-rzg2n_defconfig does not exist

Then I have added this file (r8a774b1_hihope-rzg2n_defconfig ) with content as blow:

CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-hihope-rzg2n-u-boot"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_HIHOPE_RZG2=y
# CONFIG_SPL is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a774b1-hihope-rzg2n.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_ECC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot r8a774e1-hihope-rzg2h-u-boot"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_GPIO_HOG=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_WDT=y
CONFIG_WDT_RENESAS=y
CONFIG_CMD_WDT=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y

After that u boot is build and u-boot.srec file is created and I used that for loading to boot partition 2 in EMMC.

Then following log is coming and processor is stuck

INFO:    ARM GICv2 driver initialized
NOTICE:  BL2: RZ/G2 Initial Program Loader(CA57) Rev.3.0.3
NOTICE:  BL2: PRR is RZ/G2N Ver.1.1
NOTICE:  BL2: Board is HiHope RZ/G2N Rev.2.0
NOTICE:  BL2: Boot device is eMMC(50MHz x8)
NOTICE:  BL2: DDR3200(rev.0.41)
NOTICE:  BL2: [COLD_BOOT]
NOTICE:  BL2: DRAM Split is OFF
NOTICE:  BL2: QoS is default setting(rev.0.09)
NOTICE:  BL2: DRAM refresh interval 1.95 usec
NOTICE:  BL2: Periodic Write DQ Training
NOTICE:  BL2: DRAM don't have ECC configuration
NOTICE:  BL2: CH0: 400000000 - 4ffffffff, 4 GiB
NOTICE:  BL2: Lossy Decomp areas
NOTICE:       Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
NOTICE:       Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
NOTICE:       Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
NOTICE:  BL2: FDT at 0xe631fa70
NOTICE:  BL2: v2.7(release):v2.5/rzg2l-1.00-2008-gac8a2c2f2-dirty
NOTICE:  BL2: Built : 16:59:56, Jan  4 2024
NOTICE:  BL2: Normal boot
INFO:    BL2: Doing platform setup
INFO:    BL2: Loading image id 3
NOTICE:  BL2: eMMC boot from partition 1
NOTICE:  BL2: Load dst=0xe631f300 src=(p:1)0x30000(384) len=0x200(1)
NOTICE:  BL2: Load dst=0x43f00000 src=(p:1)0x30400(386) len=0x1800(12)
WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
INFO:    Loading image id=3 at address 0x44000000
NOTICE:  rcar_file_len: len: 0x0003e000
NOTICE:  BL2: Load dst=0x44000000 src=(p:1)0x40000(512) len=0x3e000(496)
INFO:    Image id=3 loaded: 0x44000000 - 0x4403e000
INFO:    BL2: Loading image id 5
INFO:    Loading image id=5 at address 0x50000000
NOTICE:  rcar_file_len: len: 0x00100000
NOTICE:  BL2: Load dst=0x50000000 src=(p:2)0x0(0) len=0x100000(2048)
INFO:    Image id=5 loaded: 0x50000000 - 0x50100000
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0x44000000
INFO:    SPSR = 0x3cd
VERBOSE: Argument #0 = 0xe631f560
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

Please help me solve this issue.

Thanks and regards,

Kartha.

https://github.com/renesas-rz/renesas-u-boot-cip/blob/d909e2230e02e0a6251dd61e9e1f4527f6745ac1/arch/arm/dts/r8a774b1-hihope-rzg2n.dts#L22

It would be wise to create your custom dts based on that though.

I Saw this place Chris,

But I don't know how to add the size here

can you please tell me how to do that.

Or show me an example.

Thanks and regards,

Kartha.

Hi,

I have changed the dts file like this:

/ {
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";

memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;   // No change here
};

memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x00000001 0x00000000>; // Changed here = 4GB
};
};

But Still the code is stuck at the same place.

Please check this and let me know a workaround.

Thanks and regards.

Kartha

The Device Tree for the RZ/G2N HiHope board was already set for 4GB.

You did not need to change it.

/ {
    model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
    compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";

    memory@48000000 {
        device_type = "memory";
        /* first 128MB is reserved for secure area. */
        reg = <0x0 0x48000000 0x0 0x78000000>;
    };

    memory@480000000 {
        device_type = "memory";
        reg = <0x4 0x80000000 0x0 0x80000000>;
    };
};

128MB + 0x78000000 + 0x800000 = 0X100000000 (4GB)

reg = <0x0 0x48000000 0x0 0x78000000>;

This is the first 2GB of Legacy (DDR0 shadow A) (skipping over the first 128MB)

You can only map 2GB of that area. The other 2GB you have to map to the extended area

This is the 2nd half of the DDR mapped to the upper address region (DDR0)

reg = <0x4 0x80000000 0x0 0x80000000>;

Hi Chris,

I have gone through the writings.

The RAM I bought Have some problem with Rev. A, and I can only access 2 BG of data even though the RAM is 4 GB in size. 

So I have some doubts,

1. If the DTS is fixed to 4GB for RZG2N, is it feasible to to make the board up and running with a 2 GB RAM? I ask this because you have replied 

   Chris said:

   The only thing you have to change in u-boot for DDR is the size of the DDR in the Device Tree file.
2. If So what should be the memory node in DTS file?
3. I have changed the dts like below for making the entire memory to 2 GB

4. / {
   model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
   compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";

   memory@48000000 {
   device_type = "memory";
   /* first 128MB is reserved for secure area. */
   reg = <0x0 0x48000000 0x0 0x38000000>;
   };

   memory@480000000 {
   device_type = "memory";
   reg = <0x4 0x80000000 0x00000000 0x40000000>;
   };
   };

I don't know whether this is correct or not. 

Please clarify my doubts, If this RAM is not going to work with the board I need to look for another solution as soon as possible.

Thanks and regards.

Kartha.

This is 2GB of DDR.

/{
    model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
    compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";

    memory@48000000 {
        device_type = "memory";
        /* first 128MB is reserved for secure area. */
        reg = <0x0 0x48000000 0x0 0x78000000>;
    };
};    

Hi Chris

Thanks for the reply.

I have given this in my dts file (r8a774b1-hihope-rzg2n.dts)

but still stuck at DDR:

and the content of my defconfig file is shown below

CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xFFFE0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-hihope-rzg2n-u-boot"
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_HIHOPE_RZG2=y
# CONFIG_SPL is not set
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a774b1-hihope-rzg2n.dtb"
# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_BOARD_LATE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_ECC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot r8a774b1-hihope-rzg2n-u-boot r8a774e1-hihope-rzg2h-u-boot"
CONFIG_MULTI_DTB_FIT_LZO=y
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_GPIO_HOG=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_WDT=y
CONFIG_WDT_RENESAS=y
CONFIG_CMD_WDT=y
CONFIG_USB_GADGET=y
CONFIG_USB_RENESAS_USBHS=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y

I think this is correct.

This is how my dts file looks like

// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the HiHope RZ/G2N main board Rev.3.0/4.0
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/

/dts-v1/;
#include "r8a774b1.dtsi"
#include "hihope-rev4.dtsi"

/ {
model = "HopeRun HiHope RZ/G2N main board based on r8a774b1";
compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1";

memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};

// memory@480000000 {
// device_type = "memory";
// reg = <0x4 0x80000000 0x0 0x40000000>;
// };
};

&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x302_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};

&sdhi3 {
mmc-hs400-1_8v;
};

Any Idea or workaround.

Thanks for the help

Regards,

Kartha

At this point, you need to start debugging the code. You need to find the line of code that it is crashing on. Then, you can understand how to fix it.

Just changing the device tree is not going to help you.

Hi Chris,

Ok I will try that way and let you know.

Thanks for the reply.

Regards,

Kartha

Hi Chris,

I have successfully solve the issue.

The problem was with ATF, in ram configuration structure.

Now I am in u-boot shell.

I have an SD card loaded with kernel dtb and rootfs is correct partitions, which is working with my EVK board.

The same one when loaded with in the custom board and set the bootargs and bootcommand to correct location, this error is showing.

INFO: ARM GICv2 driver initialized
NOTICE: BL2: RZ/G2 Initial Program Loader(CA57) Rev.3.0.3
NOTICE: BL2: PRR is RZ/G2N Ver.1.1
NOTICE: BL2: Board is HiHope RZ/G2N Rev.2.0
NOTICE: BL2: Boot device is eMMC(50MHz x8)
NOTICE: BL2: DDR3200(rev.0.41)
NOTICE: BL2: [COLD_BOOT]
NOTICE: BL2: DRAM Split is OFF
NOTICE: BL2: QoS is default setting(rev.0.09)
NOTICE: BL2: DRAM refresh interval 1.95 usec
NOTICE: BL2: Periodic Write DQ Training
NOTICE: BL2: DRAM don't have ECC configuration
NOTICE: BL2: CH0: 400000000 - 4ffffffff, 4 GiB
NOTICE: BL2: Lossy Decomp areas
NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
NOTICE: BL2: FDT at 0xe631fa70
NOTICE: BL2: v2.7(release):v2.5/rzg2l-1.00-2008-gac8a2c2f2-dirty
NOTICE: BL2: Built : 17:59:40, Jan 9 2024
NOTICE: BL2: Normal boot
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
NOTICE: BL2: eMMC boot from partition 1
NOTICE: BL2: Load dst=0xe631f300 src=(p:1)0x30000(384) len=0x200(1)
NOTICE: BL2: Load dst=0x43f00000 src=(p:1)0x30400(386) len=0x1800(12)
WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
INFO: Loading image id=3 at address 0x44000000
NOTICE: rcar_file_len: len: 0x0003e000
NOTICE: BL2: Load dst=0x44000000 src=(p:1)0x40000(512) len=0x3e000(496)
INFO: Image id=3 loaded: 0x44000000 - 0x4403e000
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x50000000
NOTICE: rcar_file_len: len: 0x00100000
NOTICE: BL2: Load dst=0x50000000 src=(p:2)0x0(0) len=0x100000(2048)
INFO: Image id=5 loaded: 0x50000000 - 0x50100000
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0x44000000
INFO: SPSR = 0x3cd
VERBOSE: Argument #0 = 0xe631f560
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

U-Boot 2021.10-gfe9d08bec2-dirty (Jan 10 2024 - 10:46:42 +0530)

CPU: Renesas Electronics R8A774B1 rev 1.1
Model: HopeRun HiHope RZ/G2N with sub board
DRAM: 3.9 GiB
pca953x gpio@20: Error reading output register
pca953x gpio@20: Error reading output register
pca953x gpio@20: Error reading output register
pca953x gpio@20: Error reading output register
WDT: watchdog@00000000e6020000
WDT: Started with servicing (60s timeout)
MMC: mmc@ee100000: 0, mmc@ee160000: 1
Loading Environment from MMC... OK
In: serial@e6e88000
Out: serial@e6e88000
Err: serial@e6e88000
U-boot WDT started!
Net:
Error: ethernet@e6800000 address not set.
No ethernet found.

Hit any key to stop autoboot: 0
19843584 bytes read in 828 ms (22.9 MiB/s)
59483 bytes read in 5 ms (11.3 MiB/s)
Moving Image from 0x48080000 to 0x48200000, end=49560000
## Loading ramdisk from FIT Image at 48000000 ...
Bad FIT ramdisk image format! (err=-42)
Ramdisk image is corrupt or invalid

The commands I have used to set the boot device as SD card is shown below

setenv bootargs root=/dev/mmcblk1p3
setenv bootcmd "fatload mmc 0:1 0x48080000 Image; fatload mmc 0:1 0x48000000 Image-r8a774b1-hihope-rzg2n-ex.dtb; booti 0x48080000 – 0x48000000"
saveenv

Please let me know a workaround chris.

Thanks and regards,

Kartha

Kartha said:

booti 0x48080000 – 0x48000000

Check the character in between the two addresses.

There's a difference if an hyphen or a dash is used.

I have changed it Chris,

Now i stuck in another place

INFO: ARM GICv2 driver initialized
NOTICE: BL2: RZ/G2 Initial Program Loader(CA57) Rev.3.0.3
NOTICE: BL2: PRR is RZ/G2N Ver.1.1
NOTICE: BL2: Board is HiHope RZ/G2N Rev.2.0
NOTICE: BL2: Boot device is eMMC(50MHz x8)
NOTICE: BL2: DDR3200(rev.0.41)
NOTICE: BL2: [COLD_BOOT]
NOTICE: BL2: DRAM Split is OFF
NOTICE: BL2: QoS is default setting(rev.0.09)
NOTICE: BL2: DRAM refresh interval 1.95 usec
NOTICE: BL2: Periodic Write DQ Training
NOTICE: BL2: DRAM don't have ECC configuration
NOTICE: BL2: CH0: 400000000 - 4ffffffff, 4 GiB
NOTICE: BL2: Lossy Decomp areas
NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
NOTICE: BL2: FDT at 0xe631fa70
NOTICE: BL2: v2.7(release):v2.5/rzg2l-1.00-2008-gac8a2c2f2-dirty
NOTICE: BL2: Built : 17:59:40, Jan 9 2024
NOTICE: BL2: Normal boot
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
NOTICE: BL2: eMMC boot from partition 1
NOTICE: BL2: Load dst=0xe631f300 src=(p:1)0x30000(384) len=0x200(1)
NOTICE: BL2: Load dst=0x43f00000 src=(p:1)0x30400(386) len=0x1800(12)
WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
INFO: Loading image id=3 at address 0x44000000
NOTICE: rcar_file_len: len: 0x0003e000
NOTICE: BL2: Load dst=0x44000000 src=(p:1)0x40000(512) len=0x3e000(496)
INFO: Image id=3 loaded: 0x44000000 - 0x4403e000
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x50000000
NOTICE: rcar_file_len: len: 0x00100000
NOTICE: BL2: Load dst=0x50000000 src=(p:2)0x0(0) len=0x100000(2048)
INFO: Image id=5 loaded: 0x50000000 - 0x50100000
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0x44000000
INFO: SPSR = 0x3cd
VERBOSE: Argument #0 = 0xe631f560
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0

U-Boot 2021.10-gfe9d08bec2-dirty (Jan 10 2024 - 14:41:28 +0530)

CPU: Renesas Electronics R8A774B1 rev 1.1
Model: HopeRun HiHope RZ/G2N with sub board
DRAM: 3.9 GiB
pca953x gpio@20: Error reading output register
pca953x gpio@20: Error reading output register
pca953x gpio@20: Error reading output register
pca953x gpio@20: Error reading output register
WDT: watchdog@00000000e6020000
WDT: Started with servicing (60s timeout)
MMC: mmc@ee100000: 0, mmc@ee160000: 1
Loading Environment from MMC... OK
In: serial@e6e88000
Out: serial@e6e88000
Err: serial@e6e88000
U-boot WDT started!
Net:
Error: ethernet@e6800000 address not set.
No ethernet found.

Hit any key to stop autoboot: 0
19843584 bytes read in 828 ms (22.9 MiB/s)
59483 bytes read in 5 ms (11.3 MiB/s)
Moving Image from 0x48080000 to 0x48200000, end=49560000
## Flattened Device Tree blob at 48000000
Booting using the fdt blob at 0x48000000
Using Device Tree in place at 0000000048000000, end 000000004801185a
Overlap found: 0x480000000..0x4ffffffff / 0x480000000..0x4ffffffff

Starting kernel ...

The processor is stuck here..

Please help

Thanks and regards,

Kartha

Hello Team, I'm also facing similar issue on RZG2N with single channel 2GB DDR. How to fix it? Any suggestions/updates? 

bdinfo in u-boot: what is the output?

How much RAM does it report?

It resolved. issue was in peripheral initialization. DDR config was correct.

It resolved. issue was in peripheral initialization. DDR config was correct.