RZG2L RGB Interface: Sync Mode, DE Mode, and Sync-DE Modes

Hi, 

We have an RZG2L based custom PCB that is using the RGB interface peripheral in order to drive a simple and very common 480x272 TFT panel. Now we are having an issue where certain panels seem to work as expected and other 480x272 panels will either show a white screen or a black screen which is really just the backlight LED lighting up, not actual pixels being set by the RZ. 

I did some digging around and it seems that the 480x272 panels are all using the ST7282 display controller and that this controller supports the following RGB protocols, SYNC mode, SYNC-DE mode, and DE mode which is how the display controller knows when to latch onto the pixel data. I tried to review the DU subsection of the LCDC peripheral on the RZ and did not find anywhere that allows for these modes to be set. I did find the following register but it only allows for the polarities to be set on the HSYNC, VSYNC, and CLK lines.



Is there any other registers I can change in order to change the mode? My device tree and pin configuration and device nodes are exactly what the SMARC EVK has. As I mentioned the interface works with some panels, but not all and I suspect the above is there reason why however I am not sure how to switch between the modes. I have tried setting the de output mode bits but it makes no difference. 


Tony

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  • Thanks, we are adjusting PLL5 in our driver code as well. I am wondering if the registers can affect the hsync, vsync, lines separately. What I have deduced so far is that the driver is failing when trying to work with a panel using the sync signals only. If I use a panel that relies on the DE signal only, things seem to work! For reference, I am using a CLK of ~ 12.5 Mhz. 

    I will post a little later some timing data and the PLL5 CPG setting we are using. 

    Update 1:

    1. So it seems that the whole DE Mode, Sync Mode. and DE Sync Mode are panel specific and will ignore signals on the host side as necessary. 
    2. Our driver has no issues with driving a panel that using the data enable line in order to latch the pixels. 


     

  • So are you saying you are OK? Meaning, if you configure the panel to use DE then you have no display issues.

  • Sorry was not clear. I am still having issues with a panel that requires the sync signals in addition to the de signal. I am noticing that the duty cycle of the dotclk is about 66% for the pos cycle and that is outside the allowable criteria for the clk for the display controller. Are there any registers that could affect the duty cycle of the dot clk? I have tried adjusting the spread spectrum register on PLL5 but the duty cycle is still about ~66%. 

  • Guys the issue was actually with the panel I have. The power-on reset circuit was different and so much larger delay before the display controller could receive pixel data. 

    My previous comment about the clock not being 50% can also be disregarded, with the posted patch I did get a bang on 50%. 

    If anyone has a similar issue as well with their 480x272 panel. Try to assert the DISP pin after providing the panel with 3V3 after the RZ display driver has been probed. You can do this from within the RZ display driver inside the enable method. 

    Closing ticket, thanks!