• State Verified Answer
  • +1 person also asked this people also asked this
  • Replies 5 replies
  • Subscribers 577 subscribers
  • Views 1358 views
  • Users 0 members are here
Options
Related

RZN1D reset issue

Sreehari

Hi All,

We have accommodated RZN1D series-based MPU R9A06G032NGBG#AC1 in our design. We are at the pre-production phase and this issue caught our attention, need your extreme support to close this issue.

Issue description:

The system is not resetting and hanging in the following conditions. 
1. While pressing reset button.

2. Randomly when the application runs.

Schematics snapshots

Reset (green) waveform at normal condition 

Reset (green) waveform while getting stuck/ Hang

We have observed that the reset lines are properly functional in all conditions. Please let us know if there is any known issues or work arounds for the same or else we need a technical discussion with your SMEs to resolve the issue 

Parents Reply
  • +1 in reply to Sreehari

    Hi Sreehari,

       > Please share the code with us so that we can optimize the same.

    Please check the RZN1 Solutioin Kit Package folder YCONNECT-IT-RZN_V1.4.x\Documents\RZN.Boards\RZN1D-DB. The zip file RZ_N1D_DB_Lattice_PMU.V600.zip holds the actual PMU POWR605 PMIC data base from Lattice.

    This file is listed in the related top level document Readme.Release.V14x.pdf inside the Solution Kit package.
    Or is something missing in this Lattice PMU Programming Data Base?

    Best regards,
      Andreas

Children
  • 0 in reply to Andreas Schwope

    Hi,

    We have received the POWR605 PMIC code from the RZN1 Solution Kit Package folder. Based on the code, it is clear that the PMIC reinitiates the power-up sequence in response to any local or master reset input. If a power rail exceeds its lower or upper limit, the core powers are disabled, and the PMIC holds the reset line low, entering a halt state. This results in the processor remaining in a reset state until the main power is recycled.

    1. Why is the halt option implemented in the code instead of automatically rebooting the processor once the voltage levels are within normal range?

    Since we are moving forward with a product design, we are considering modifying the code so that, in the event of a power disturbance, the PMIC would restart the MPU rather than entering the halt state.

    2. We would appreciate your insights on the planned changes to the PMIC behavior.

    Thanks in advance

    Melbin

  • 0 in reply to Melbin

    Hi Melbin,

    - The RZN1x boards are evaluation boards only. With this there are a lot of evaluation related items which partially should not be copied from the evaluation board.
    - The POWR605 PMIC implementation is related to evaluation board aspect and probably does not match to concrete product requirements of all customers. There is never a one-size-fits-all, customers need to implement according to their concrete requirements.

    There is not such a plan to modify this board.Basically the RZN1x-DB designs are evaluation boards and their schematics including the used power circuitry always needs to be aligned/designed/adjusted to customer board requirements.

    Kind Regards.