Hi,
I want to halt the Global System Counter for debugging purposes which I enabled in the respective register with the .HDBG bit.
However, the status bit .DBGH for monitoring this setting does not change which for me is an indication that it is not working as I intended.
I attached a screenshot of the corresponding registers.
Can someone help me with this?
Kind regards.
HI Mike,First of all your query is mostly related to ARM architecture and is not specific to RZ/T2M.Are you interested specifically for the Cortex-R system counter behavior?Please note there are difference between Cortex-A and Cortex-R architectures.Taking as a reference the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R:
The DBGDSCR (Debug Status and Control Register) and DBGPRCR (Debug Power Control Register) are critical for configuring debug behavior in ARM Cortex-R processors, including the handling of CPU halt states, external debug access, and peripheral behavior during debugging.Kind Regards.
I didn't know that it is a setting on the processor level, so thanks for clarification.
I am using the Renesas LSI R9A07G075M26 with two Cortex-R52 which has two cores respectively. So after reading your explanation, I looked for the ARMv8-R 32bit Architecture reference manual. I found the reference manual for A-profiles of v8 upwards (DDI 0487) and the Armv8-R supplement document (DDI 0568) though I couldn't find any tables resembling yours on your screenshots. But even if I did, I unfortunately don't know how to access the Cortex registers in code.
My team is developing on e2studio with the FSP v2.0.0. , so we are building on the infastructure that Renesas already provided. Can you please tell me what I must do to achieve the scenario 'CPU stopped in debug'?
Kind Regards.
Hi Mike,As already mentioned this is an advanced topic that requires knowledge from ARM's coresight.If you want more info please contact with ARM to provide you the required documents and information you need.Kind Regards.